1/* 2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2007-2009 PetaLogix 4 * Copyright (C) 2006 Atmark Techno, Inc. 5 * 6 * MMU code derived from arch/ppc/kernel/head_4xx.S: 7 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> 8 * Initial PowerPC version. 9 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> 10 * Rewritten for PReP 11 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 12 * Low-level exception handers, MMU support, and rewrite. 13 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> 14 * PowerPC 8xx modifications. 15 * Copyright (c) 1998-1999 TiVo, Inc. 16 * PowerPC 403GCX modifications. 17 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 18 * PowerPC 403GCX/405GP modifications. 19 * Copyright 2000 MontaVista Software Inc. 20 * PPC405 modifications 21 * PowerPC 403GCX/405GP modifications. 22 * Author: MontaVista Software, Inc. 23 * frank_rowand@mvista.com or source@mvista.com 24 * debbie_chu@mvista.com 25 * 26 * This file is subject to the terms and conditions of the GNU General Public 27 * License. See the file "COPYING" in the main directory of this archive 28 * for more details. 29 */ 30 31#include <linux/linkage.h> 32#include <asm/thread_info.h> 33#include <asm/page.h> 34#include <linux/of_fdt.h> /* for OF_DT_HEADER */ 35 36#ifdef CONFIG_MMU 37#include <asm/setup.h> /* COMMAND_LINE_SIZE */ 38#include <asm/mmu.h> 39#include <asm/processor.h> 40 41.data 42.global empty_zero_page 43.align 12 44empty_zero_page: 45 .space 4096 46.global swapper_pg_dir 47swapper_pg_dir: 48 .space 4096 49 50#endif /* CONFIG_MMU */ 51 52 .text 53ENTRY(_start) 54 mfs r1, rmsr 55 andi r1, r1, ~2 56 mts rmsr, r1 57/* 58 * Here is checking mechanism which check if Microblaze has msr instructions 59 * We load msr and compare it with previous r1 value - if is the same, 60 * msr instructions works if not - cpu don't have them. 61 */ 62 /* r8=0 - I have msr instr, 1 - I don't have them */ 63 rsubi r0, r0, 1 /* set the carry bit */ 64 msrclr r0, 0x4 /* try to clear it */ 65 /* read the carry bit, r8 will be '0' if msrclr exists */ 66 addik r8, r0, 0 67 68/* r7 may point to an FDT, or there may be one linked in. 69 if it's in r7, we've got to save it away ASAP. 70 We ensure r7 points to a valid FDT, just in case the bootloader 71 is broken or non-existent */ 72 beqi r7, no_fdt_arg /* NULL pointer? don't copy */ 73 lw r11, r0, r7 /* Does r7 point to a */ 74 rsubi r11, r11, OF_DT_HEADER /* valid FDT? */ 75 beqi r11, _prepare_copy_fdt 76 or r7, r0, r0 /* clear R7 when not valid DTB */ 77 bnei r11, no_fdt_arg /* No - get out of here */ 78_prepare_copy_fdt: 79 or r11, r0, r0 /* incremment */ 80 ori r4, r0, TOPHYS(_fdt_start) 81 ori r3, r0, (0x4000 - 4) 82_copy_fdt: 83 lw r12, r7, r11 /* r12 = r7 + r11 */ 84 sw r12, r4, r11 /* addr[r4 + r11] = r12 */ 85 addik r11, r11, 4 /* increment counting */ 86 bgtid r3, _copy_fdt /* loop for all entries */ 87 addik r3, r3, -4 /* descrement loop */ 88no_fdt_arg: 89 90#ifdef CONFIG_MMU 91 92#ifndef CONFIG_CMDLINE_BOOL 93/* 94 * handling command line 95 * copy command line to __init_end. There is space for storing command line. 96 */ 97 or r6, r0, r0 /* incremment */ 98 ori r4, r0, __init_end /* load address of command line */ 99 tophys(r4,r4) /* convert to phys address */ 100 ori r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */ 101_copy_command_line: 102 lbu r7, r5, r6 /* r7=r5+r6 - r5 contain pointer to command line */ 103 sb r7, r4, r6 /* addr[r4+r6]= r7*/ 104 addik r6, r6, 1 /* increment counting */ 105 bgtid r3, _copy_command_line /* loop for all entries */ 106 addik r3, r3, -1 /* descrement loop */ 107 addik r5, r4, 0 /* add new space for command line */ 108 tovirt(r5,r5) 109#endif /* CONFIG_CMDLINE_BOOL */ 110 111#ifdef NOT_COMPILE 112/* save bram context */ 113 or r6, r0, r0 /* incremment */ 114 ori r4, r0, TOPHYS(_bram_load_start) /* save bram context */ 115 ori r3, r0, (LMB_SIZE - 4) 116_copy_bram: 117 lw r7, r0, r6 /* r7 = r0 + r6 */ 118 sw r7, r4, r6 /* addr[r4 + r6] = r7*/ 119 addik r6, r6, 4 /* increment counting */ 120 bgtid r3, _copy_bram /* loop for all entries */ 121 addik r3, r3, -4 /* descrement loop */ 122#endif 123 /* We have to turn on the MMU right away. */ 124 125 /* 126 * Set up the initial MMU state so we can do the first level of 127 * kernel initialization. This maps the first 16 MBytes of memory 1:1 128 * virtual to physical. 129 */ 130 nop 131 addik r3, r0, 63 /* Invalidate all TLB entries */ 132_invalidate: 133 mts rtlbx, r3 134 mts rtlbhi, r0 /* flush: ensure V is clear */ 135 bgtid r3, _invalidate /* loop for all entries */ 136 addik r3, r3, -1 137 /* sync */ 138 139 /* 140 * We should still be executing code at physical address area 141 * RAM_BASEADDR at this point. However, kernel code is at 142 * a virtual address. So, set up a TLB mapping to cover this once 143 * translation is enabled. 144 */ 145 146 addik r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */ 147 tophys(r4,r3) /* Load the kernel physical address */ 148 149 mts rpid,r0 /* Load the kernel PID */ 150 nop 151 bri 4 152 153 /* 154 * Configure and load two entries into TLB slots 0 and 1. 155 * In case we are pinning TLBs, these are reserved in by the 156 * other TLB functions. If not reserving, then it doesn't 157 * matter where they are loaded. 158 */ 159 andi r4,r4,0xfffffc00 /* Mask off the real page number */ 160 ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */ 161 162 andi r3,r3,0xfffffc00 /* Mask off the effective page number */ 163 ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M)) 164 165 mts rtlbx,r0 /* TLB slow 0 */ 166 167 mts rtlblo,r4 /* Load the data portion of the entry */ 168 mts rtlbhi,r3 /* Load the tag portion of the entry */ 169 170 addik r4, r4, 0x01000000 /* Map next 16 M entries */ 171 addik r3, r3, 0x01000000 172 173 ori r6,r0,1 /* TLB slot 1 */ 174 mts rtlbx,r6 175 176 mts rtlblo,r4 /* Load the data portion of the entry */ 177 mts rtlbhi,r3 /* Load the tag portion of the entry */ 178 179 /* 180 * Load a TLB entry for LMB, since we need access to 181 * the exception vectors, using a 4k real==virtual mapping. 182 */ 183 ori r6,r0,3 /* TLB slot 3 */ 184 mts rtlbx,r6 185 186 ori r4,r0,(TLB_WR | TLB_EX) 187 ori r3,r0,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K)) 188 189 mts rtlblo,r4 /* Load the data portion of the entry */ 190 mts rtlbhi,r3 /* Load the tag portion of the entry */ 191 192 /* 193 * We now have the lower 16 Meg of RAM mapped into TLB entries, and the 194 * caches ready to work. 195 */ 196turn_on_mmu: 197 ori r15,r0,start_here 198 ori r4,r0,MSR_KERNEL_VMS 199 mts rmsr,r4 200 nop 201 rted r15,0 /* enables MMU */ 202 nop 203 204start_here: 205#endif /* CONFIG_MMU */ 206 207 /* Initialize small data anchors */ 208 la r13, r0, _KERNEL_SDA_BASE_ 209 la r2, r0, _KERNEL_SDA2_BASE_ 210 211 /* Initialize stack pointer */ 212 la r1, r0, init_thread_union + THREAD_SIZE - 4 213 214 /* Initialize r31 with current task address */ 215 la r31, r0, init_task 216 217 /* 218 * Call platform dependent initialize function. 219 * Please see $(ARCH)/mach-$(SUBARCH)/setup.c for 220 * the function. 221 */ 222 la r9, r0, machine_early_init 223 brald r15, r9 224 nop 225 226#ifndef CONFIG_MMU 227 la r15, r0, machine_halt 228 braid start_kernel 229 nop 230#else 231 /* 232 * Initialize the MMU. 233 */ 234 bralid r15, mmu_init 235 nop 236 237 /* Go back to running unmapped so we can load up new values 238 * and change to using our exception vectors. 239 * On the MicroBlaze, all we invalidate the used TLB entries to clear 240 * the old 16M byte TLB mappings. 241 */ 242 ori r15,r0,TOPHYS(kernel_load_context) 243 ori r4,r0,MSR_KERNEL 244 mts rmsr,r4 245 nop 246 bri 4 247 rted r15,0 248 nop 249 250 /* Load up the kernel context */ 251kernel_load_context: 252 # Keep entry 0 and 1 valid. Entry 3 mapped to LMB can go away. 253 ori r5,r0,3 254 mts rtlbx,r5 255 nop 256 mts rtlbhi,r0 257 nop 258 addi r15, r0, machine_halt 259 ori r17, r0, start_kernel 260 ori r4, r0, MSR_KERNEL_VMS 261 mts rmsr, r4 262 nop 263 rted r17, 0 /* enable MMU and jump to start_kernel */ 264 nop 265#endif /* CONFIG_MMU */ 266