1 /* 2 * Support for MicroBlaze PVR (processor version register) 3 * 4 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> 5 * Copyright (C) 2007-2009 PetaLogix 6 * Copyright (C) 2007 John Williams <john.williams@petalogix.com> 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 13 #include <linux/init.h> 14 #include <linux/string.h> 15 #include <asm/pvr.h> 16 #include <asm/cpuinfo.h> 17 18 /* 19 * Helper macro to map between fields in our struct cpuinfo, and 20 * the PVR macros in pvr.h. 21 */ 22 23 #define CI(c, p) { ci->c = PVR_##p(pvr); } 24 #define err_printk(x) \ 25 early_printk("ERROR: Microblaze " x " - different for PVR and DTS\n"); 26 27 void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu) 28 { 29 struct pvr_s pvr; 30 int temp; /* for saving temp value */ 31 get_pvr(&pvr); 32 33 temp = PVR_USE_BARREL(pvr) | PVR_USE_MSR_INSTR(pvr) |\ 34 PVR_USE_PCMP_INSTR(pvr) | PVR_USE_DIV(pvr); 35 if (ci->use_instr != temp) 36 err_printk("BARREL, MSR, PCMP or DIV"); 37 ci->use_instr = temp; 38 39 temp = PVR_USE_HW_MUL(pvr) | PVR_USE_MUL64(pvr); 40 if (ci->use_mult != temp) 41 err_printk("HW_MUL"); 42 ci->use_mult = temp; 43 44 temp = PVR_USE_FPU(pvr) | PVR_USE_FPU2(pvr); 45 if (ci->use_fpu != temp) 46 err_printk("HW_FPU"); 47 ci->use_fpu = temp; 48 49 ci->use_exc = PVR_OPCODE_0x0_ILLEGAL(pvr) |\ 50 PVR_UNALIGNED_EXCEPTION(pvr) |\ 51 PVR_ILL_OPCODE_EXCEPTION(pvr) |\ 52 PVR_IOPB_BUS_EXCEPTION(pvr) |\ 53 PVR_DOPB_BUS_EXCEPTION(pvr) |\ 54 PVR_DIV_ZERO_EXCEPTION(pvr) |\ 55 PVR_FPU_EXCEPTION(pvr) |\ 56 PVR_FSL_EXCEPTION(pvr); 57 58 CI(pvr_user1, USER1); 59 CI(pvr_user2, USER2); 60 61 CI(mmu, USE_MMU); 62 63 CI(ver_code, VERSION); 64 65 CI(use_icache, USE_ICACHE); 66 CI(icache_tagbits, ICACHE_ADDR_TAG_BITS); 67 CI(icache_write, ICACHE_ALLOW_WR); 68 CI(icache_line, ICACHE_LINE_LEN); 69 CI(icache_size, ICACHE_BYTE_SIZE); 70 CI(icache_base, ICACHE_BASEADDR); 71 CI(icache_high, ICACHE_HIGHADDR); 72 73 CI(use_dcache, USE_DCACHE); 74 CI(dcache_tagbits, DCACHE_ADDR_TAG_BITS); 75 CI(dcache_write, DCACHE_ALLOW_WR); 76 CI(dcache_line, DCACHE_LINE_LEN); 77 CI(dcache_size, DCACHE_BYTE_SIZE); 78 CI(dcache_base, DCACHE_BASEADDR); 79 CI(dcache_high, DCACHE_HIGHADDR); 80 81 CI(use_dopb, D_OPB); 82 CI(use_iopb, I_OPB); 83 CI(use_dlmb, D_LMB); 84 CI(use_ilmb, I_LMB); 85 CI(num_fsl, FSL_LINKS); 86 87 CI(irq_edge, INTERRUPT_IS_EDGE); 88 CI(irq_positive, EDGE_IS_POSITIVE); 89 90 CI(area_optimised, AREA_OPTIMISED); 91 92 CI(hw_debug, DEBUG_ENABLED); 93 CI(num_pc_brk, NUMBER_OF_PC_BRK); 94 CI(num_rd_brk, NUMBER_OF_RD_ADDR_BRK); 95 CI(num_wr_brk, NUMBER_OF_WR_ADDR_BRK); 96 97 CI(fpga_family_code, TARGET_FAMILY); 98 99 /* take timebase-frequency from DTS */ 100 ci->cpu_clock_freq = fcpu(cpu, "timebase-frequency"); 101 } 102