1 /* 2 * Support for the MicroBlaze PVR (Processor Version Register) 3 * 4 * Copyright (C) 2009 Michal Simek <monstr@monstr.eu> 5 * Copyright (C) 2007 John Williams <john.williams@petalogix.com> 6 * Copyright (C) 2007 - 2009 PetaLogix 7 * 8 * This file is subject to the terms and conditions of the GNU General 9 * Public License. See the file COPYING in the main directory of this 10 * archive for more details. 11 */ 12 13 #ifndef _ASM_MICROBLAZE_PVR_H 14 #define _ASM_MICROBLAZE_PVR_H 15 16 #define PVR_MSR_BIT 0x400 17 18 struct pvr_s { 19 unsigned pvr[16]; 20 }; 21 22 /* The following taken from Xilinx's standalone BSP pvr.h */ 23 24 /* Basic PVR mask */ 25 #define PVR0_PVR_FULL_MASK 0x80000000 26 #define PVR0_USE_BARREL_MASK 0x40000000 27 #define PVR0_USE_DIV_MASK 0x20000000 28 #define PVR0_USE_HW_MUL_MASK 0x10000000 29 #define PVR0_USE_FPU_MASK 0x08000000 30 #define PVR0_USE_EXC_MASK 0x04000000 31 #define PVR0_USE_ICACHE_MASK 0x02000000 32 #define PVR0_USE_DCACHE_MASK 0x01000000 33 #define PVR0_USE_MMU 0x00800000 /* new */ 34 #define PVR0_VERSION_MASK 0x0000FF00 35 #define PVR0_USER1_MASK 0x000000FF 36 37 /* User 2 PVR mask */ 38 #define PVR1_USER2_MASK 0xFFFFFFFF 39 40 /* Configuration PVR masks */ 41 #define PVR2_D_OPB_MASK 0x80000000 42 #define PVR2_D_LMB_MASK 0x40000000 43 #define PVR2_I_OPB_MASK 0x20000000 44 #define PVR2_I_LMB_MASK 0x10000000 45 #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000 46 #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000 47 #define PVR2_D_PLB_MASK 0x02000000 /* new */ 48 #define PVR2_I_PLB_MASK 0x01000000 /* new */ 49 #define PVR2_INTERCONNECT 0x00800000 /* new */ 50 #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */ 51 #define PVR2_USE_FSL_EXC 0x00040000 /* new */ 52 #define PVR2_USE_MSR_INSTR 0x00020000 53 #define PVR2_USE_PCMP_INSTR 0x00010000 54 #define PVR2_AREA_OPTIMISED 0x00008000 55 #define PVR2_USE_BARREL_MASK 0x00004000 56 #define PVR2_USE_DIV_MASK 0x00002000 57 #define PVR2_USE_HW_MUL_MASK 0x00001000 58 #define PVR2_USE_FPU_MASK 0x00000800 59 #define PVR2_USE_MUL64_MASK 0x00000400 60 #define PVR2_USE_FPU2_MASK 0x00000200 /* new */ 61 #define PVR2_USE_IPLBEXC 0x00000100 62 #define PVR2_USE_DPLBEXC 0x00000080 63 #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040 64 #define PVR2_UNALIGNED_EXC_MASK 0x00000020 65 #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010 66 #define PVR2_IOPB_BUS_EXC_MASK 0x00000008 67 #define PVR2_DOPB_BUS_EXC_MASK 0x00000004 68 #define PVR2_DIV_ZERO_EXC_MASK 0x00000002 69 #define PVR2_FPU_EXC_MASK 0x00000001 70 71 /* Debug and exception PVR masks */ 72 #define PVR3_DEBUG_ENABLED_MASK 0x80000000 73 #define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000 74 #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000 75 #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000 76 #define PVR3_FSL_LINKS_MASK 0x00000380 77 78 /* ICache config PVR masks */ 79 #define PVR4_USE_ICACHE_MASK 0x80000000 80 #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000 81 #define PVR4_ICACHE_USE_FSL_MASK 0x02000000 82 #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000 83 #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 84 #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 85 86 /* DCache config PVR masks */ 87 #define PVR5_USE_DCACHE_MASK 0x80000000 88 #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000 89 #define PVR5_DCACHE_USE_FSL_MASK 0x02000000 90 #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 91 #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 92 #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 93 94 /* ICache base address PVR mask */ 95 #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF 96 97 /* ICache high address PVR mask */ 98 #define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF 99 100 /* DCache base address PVR mask */ 101 #define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF 102 103 /* DCache high address PVR mask */ 104 #define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF 105 106 /* Target family PVR mask */ 107 #define PVR10_TARGET_FAMILY_MASK 0xFF000000 108 109 /* MMU descrtiption */ 110 #define PVR11_USE_MMU 0xC0000000 111 #define PVR11_MMU_ITLB_SIZE 0x38000000 112 #define PVR11_MMU_DTLB_SIZE 0x07000000 113 #define PVR11_MMU_TLB_ACCESS 0x00C00000 114 #define PVR11_MMU_ZONES 0x003C0000 115 /* MSR Reset value PVR mask */ 116 #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF 117 118 119 /* PVR access macros */ 120 #define PVR_IS_FULL(pvr) (pvr.pvr[0] & PVR0_PVR_FULL_MASK) 121 #define PVR_USE_BARREL(pvr) (pvr.pvr[0] & PVR0_USE_BARREL_MASK) 122 #define PVR_USE_DIV(pvr) (pvr.pvr[0] & PVR0_USE_DIV_MASK) 123 #define PVR_USE_HW_MUL(pvr) (pvr.pvr[0] & PVR0_USE_HW_MUL_MASK) 124 #define PVR_USE_FPU(pvr) (pvr.pvr[0] & PVR0_USE_FPU_MASK) 125 #define PVR_USE_FPU2(pvr) (pvr.pvr[2] & PVR2_USE_FPU2_MASK) 126 #define PVR_USE_ICACHE(pvr) (pvr.pvr[0] & PVR0_USE_ICACHE_MASK) 127 #define PVR_USE_DCACHE(pvr) (pvr.pvr[0] & PVR0_USE_DCACHE_MASK) 128 #define PVR_VERSION(pvr) ((pvr.pvr[0] & PVR0_VERSION_MASK) >> 8) 129 #define PVR_USER1(pvr) (pvr.pvr[0] & PVR0_USER1_MASK) 130 #define PVR_USER2(pvr) (pvr.pvr[1] & PVR1_USER2_MASK) 131 132 #define PVR_D_OPB(pvr) (pvr.pvr[2] & PVR2_D_OPB_MASK) 133 #define PVR_D_LMB(pvr) (pvr.pvr[2] & PVR2_D_LMB_MASK) 134 #define PVR_I_OPB(pvr) (pvr.pvr[2] & PVR2_I_OPB_MASK) 135 #define PVR_I_LMB(pvr) (pvr.pvr[2] & PVR2_I_LMB_MASK) 136 #define PVR_INTERRUPT_IS_EDGE(pvr) \ 137 (pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK) 138 #define PVR_EDGE_IS_POSITIVE(pvr) \ 139 (pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK) 140 #define PVR_USE_MSR_INSTR(pvr) (pvr.pvr[2] & PVR2_USE_MSR_INSTR) 141 #define PVR_USE_PCMP_INSTR(pvr) (pvr.pvr[2] & PVR2_USE_PCMP_INSTR) 142 #define PVR_AREA_OPTIMISED(pvr) (pvr.pvr[2] & PVR2_AREA_OPTIMISED) 143 #define PVR_USE_MUL64(pvr) (pvr.pvr[2] & PVR2_USE_MUL64_MASK) 144 #define PVR_OPCODE_0x0_ILLEGAL(pvr) \ 145 (pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK) 146 #define PVR_UNALIGNED_EXCEPTION(pvr) \ 147 (pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK) 148 #define PVR_ILL_OPCODE_EXCEPTION(pvr) \ 149 (pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK) 150 #define PVR_IOPB_BUS_EXCEPTION(pvr) \ 151 (pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK) 152 #define PVR_DOPB_BUS_EXCEPTION(pvr) \ 153 (pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK) 154 #define PVR_DIV_ZERO_EXCEPTION(pvr) \ 155 (pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK) 156 #define PVR_FPU_EXCEPTION(pvr) (pvr.pvr[2] & PVR2_FPU_EXC_MASK) 157 #define PVR_FSL_EXCEPTION(pvr) (pvr.pvr[2] & PVR2_USE_EXTEND_FSL) 158 159 #define PVR_DEBUG_ENABLED(pvr) (pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK) 160 #define PVR_NUMBER_OF_PC_BRK(pvr) \ 161 ((pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25) 162 #define PVR_NUMBER_OF_RD_ADDR_BRK(pvr) \ 163 ((pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19) 164 #define PVR_NUMBER_OF_WR_ADDR_BRK(pvr) \ 165 ((pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13) 166 #define PVR_FSL_LINKS(pvr) ((pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7) 167 168 #define PVR_ICACHE_ADDR_TAG_BITS(pvr) \ 169 ((pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26) 170 #define PVR_ICACHE_USE_FSL(pvr) (pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK) 171 #define PVR_ICACHE_ALLOW_WR(pvr) (pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK) 172 #define PVR_ICACHE_LINE_LEN(pvr) \ 173 (1 << ((pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21)) 174 #define PVR_ICACHE_BYTE_SIZE(pvr) \ 175 (1 << ((pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16)) 176 177 #define PVR_DCACHE_ADDR_TAG_BITS(pvr) \ 178 ((pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26) 179 #define PVR_DCACHE_USE_FSL(pvr) (pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK) 180 #define PVR_DCACHE_ALLOW_WR(pvr) (pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK) 181 #define PVR_DCACHE_LINE_LEN(pvr) \ 182 (1 << ((pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21)) 183 #define PVR_DCACHE_BYTE_SIZE(pvr) \ 184 (1 << ((pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16)) 185 186 187 #define PVR_ICACHE_BASEADDR(pvr) (pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK) 188 #define PVR_ICACHE_HIGHADDR(pvr) (pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK) 189 190 #define PVR_DCACHE_BASEADDR(pvr) (pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK) 191 #define PVR_DCACHE_HIGHADDR(pvr) (pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK) 192 193 #define PVR_TARGET_FAMILY(pvr) ((pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24) 194 195 #define PVR_MSR_RESET_VALUE(pvr) \ 196 (pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK) 197 198 /* mmu */ 199 #define PVR_USE_MMU(pvr) ((pvr.pvr[11] & PVR11_USE_MMU) >> 30) 200 #define PVR_MMU_ITLB_SIZE(pvr) (pvr.pvr[11] & PVR11_MMU_ITLB_SIZE) 201 #define PVR_MMU_DTLB_SIZE(pvr) (pvr.pvr[11] & PVR11_MMU_DTLB_SIZE) 202 #define PVR_MMU_TLB_ACCESS(pvr) (pvr.pvr[11] & PVR11_MMU_TLB_ACCESS) 203 #define PVR_MMU_ZONES(pvr) (pvr.pvr[11] & PVR11_MMU_ZONES) 204 205 206 int cpu_has_pvr(void); 207 void get_pvr(struct pvr_s *pvr); 208 209 #endif /* _ASM_MICROBLAZE_PVR_H */ 210