1 #ifndef _ASM_MICROBLAZE_PCI_BRIDGE_H 2 #define _ASM_MICROBLAZE_PCI_BRIDGE_H 3 #ifdef __KERNEL__ 4 /* 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 */ 10 #include <linux/pci.h> 11 #include <linux/list.h> 12 #include <linux/ioport.h> 13 #include <asm-generic/pci-bridge.h> 14 15 struct device_node; 16 17 #ifdef CONFIG_PCI 18 extern struct list_head hose_list; 19 extern int pcibios_vaddr_is_ioport(void __iomem *address); 20 #else 21 static inline int pcibios_vaddr_is_ioport(void __iomem *address) 22 { 23 return 0; 24 } 25 #endif 26 27 /* 28 * Structure of a PCI controller (host bridge) 29 */ 30 struct pci_controller { 31 struct pci_bus *bus; 32 char is_dynamic; 33 struct device_node *dn; 34 struct list_head list_node; 35 struct device *parent; 36 37 int first_busno; 38 int last_busno; 39 40 int self_busno; 41 42 void __iomem *io_base_virt; 43 resource_size_t io_base_phys; 44 45 resource_size_t pci_io_size; 46 47 /* Some machines (PReP) have a non 1:1 mapping of 48 * the PCI memory space in the CPU bus space 49 */ 50 resource_size_t pci_mem_offset; 51 52 /* Some machines have a special region to forward the ISA 53 * "memory" cycles such as VGA memory regions. Left to 0 54 * if unsupported 55 */ 56 resource_size_t isa_mem_phys; 57 resource_size_t isa_mem_size; 58 59 struct pci_ops *ops; 60 unsigned int __iomem *cfg_addr; 61 void __iomem *cfg_data; 62 63 /* 64 * Used for variants of PCI indirect handling and possible quirks: 65 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 66 * EXT_REG - provides access to PCI-e extended registers 67 * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS 68 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS 69 * to determine which bus number to match on when generating type0 70 * config cycles 71 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with 72 * hanging if we don't have link and try to do config cycles to 73 * anything but the PHB. Only allow talking to the PHB if this is 74 * set. 75 * BIG_ENDIAN - cfg_addr is a big endian register 76 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs 77 * on the PLB4. Effectively disable MRM commands by setting this. 78 */ 79 #define INDIRECT_TYPE_SET_CFG_TYPE 0x00000001 80 #define INDIRECT_TYPE_EXT_REG 0x00000002 81 #define INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004 82 #define INDIRECT_TYPE_NO_PCIE_LINK 0x00000008 83 #define INDIRECT_TYPE_BIG_ENDIAN 0x00000010 84 #define INDIRECT_TYPE_BROKEN_MRM 0x00000020 85 u32 indirect_type; 86 87 /* Currently, we limit ourselves to 1 IO range and 3 mem 88 * ranges since the common pci_bus structure can't handle more 89 */ 90 struct resource io_resource; 91 struct resource mem_resources[3]; 92 int global_number; /* PCI domain number */ 93 }; 94 95 #ifdef CONFIG_PCI 96 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) 97 { 98 return bus->sysdata; 99 } 100 101 static inline int isa_vaddr_is_ioport(void __iomem *address) 102 { 103 /* No specific ISA handling on ppc32 at this stage, it 104 * all goes through PCI 105 */ 106 return 0; 107 } 108 #endif /* CONFIG_PCI */ 109 110 /* These are used for config access before all the PCI probing 111 has been done. */ 112 extern int early_read_config_byte(struct pci_controller *hose, int bus, 113 int dev_fn, int where, u8 *val); 114 extern int early_read_config_word(struct pci_controller *hose, int bus, 115 int dev_fn, int where, u16 *val); 116 extern int early_read_config_dword(struct pci_controller *hose, int bus, 117 int dev_fn, int where, u32 *val); 118 extern int early_write_config_byte(struct pci_controller *hose, int bus, 119 int dev_fn, int where, u8 val); 120 extern int early_write_config_word(struct pci_controller *hose, int bus, 121 int dev_fn, int where, u16 val); 122 extern int early_write_config_dword(struct pci_controller *hose, int bus, 123 int dev_fn, int where, u32 val); 124 125 extern int early_find_capability(struct pci_controller *hose, int bus, 126 int dev_fn, int cap); 127 128 extern void setup_indirect_pci(struct pci_controller *hose, 129 resource_size_t cfg_addr, 130 resource_size_t cfg_data, u32 flags); 131 132 /* Get the PCI host controller for an OF device */ 133 extern struct pci_controller *pci_find_hose_for_OF_device( 134 struct device_node *node); 135 136 /* Fill up host controller resources from the OF node */ 137 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose, 138 struct device_node *dev, int primary); 139 140 /* Allocate & free a PCI host bridge structure */ 141 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev); 142 extern void pcibios_free_controller(struct pci_controller *phb); 143 extern void pcibios_setup_phb_resources(struct pci_controller *hose); 144 145 #endif /* __KERNEL__ */ 146 #endif /* _ASM_MICROBLAZE_PCI_BRIDGE_H */ 147