1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Device Tree Generator version: 1.1 4 * 5 * (C) Copyright 2007-2008 Xilinx, Inc. 6 * (C) Copyright 2007-2009 Michal Simek 7 * 8 * Michal SIMEK <monstr@monstr.eu> 9 * 10 * CAUTION: This file is automatically generated by libgen. 11 * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6 12 * 13 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101 14 */ 15 16/dts-v1/; 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 compatible = "xlnx,microblaze"; 21 hard-reset-gpios = <&LEDs_8Bit 2 1>; 22 model = "testing"; 23 DDR2_SDRAM: memory@90000000 { 24 device_type = "memory"; 25 reg = < 0x90000000 0x10000000 >; 26 } ; 27 aliases { 28 ethernet0 = &Hard_Ethernet_MAC; 29 serial0 = &RS232_Uart_1; 30 } ; 31 chosen { 32 bootargs = "console=ttyUL0,115200 highres=on"; 33 stdout-path = "/plb@0/serial@84000000"; 34 } ; 35 cpus { 36 #address-cells = <1>; 37 #cpus = <0x1>; 38 #size-cells = <0>; 39 microblaze_0: cpu@0 { 40 clock-frequency = <125000000>; 41 compatible = "xlnx,microblaze-7.10.d"; 42 d-cache-baseaddr = <0x90000000>; 43 d-cache-highaddr = <0x9fffffff>; 44 d-cache-line-size = <0x10>; 45 d-cache-size = <0x2000>; 46 device_type = "cpu"; 47 i-cache-baseaddr = <0x90000000>; 48 i-cache-highaddr = <0x9fffffff>; 49 i-cache-line-size = <0x10>; 50 i-cache-size = <0x2000>; 51 model = "microblaze,7.10.d"; 52 reg = <0>; 53 timebase-frequency = <125000000>; 54 xlnx,addr-tag-bits = <0xf>; 55 xlnx,allow-dcache-wr = <0x1>; 56 xlnx,allow-icache-wr = <0x1>; 57 xlnx,area-optimized = <0x0>; 58 xlnx,cache-byte-size = <0x2000>; 59 xlnx,d-lmb = <0x1>; 60 xlnx,d-opb = <0x0>; 61 xlnx,d-plb = <0x1>; 62 xlnx,data-size = <0x20>; 63 xlnx,dcache-addr-tag = <0xf>; 64 xlnx,dcache-always-used = <0x1>; 65 xlnx,dcache-byte-size = <0x2000>; 66 xlnx,dcache-line-len = <0x4>; 67 xlnx,dcache-use-fsl = <0x1>; 68 xlnx,debug-enabled = <0x1>; 69 xlnx,div-zero-exception = <0x1>; 70 xlnx,dopb-bus-exception = <0x0>; 71 xlnx,dynamic-bus-sizing = <0x1>; 72 xlnx,edge-is-positive = <0x1>; 73 xlnx,family = "virtex5"; 74 xlnx,endianness = <0x1>; 75 xlnx,fpu-exception = <0x1>; 76 xlnx,fsl-data-size = <0x20>; 77 xlnx,fsl-exception = <0x0>; 78 xlnx,fsl-links = <0x0>; 79 xlnx,i-lmb = <0x1>; 80 xlnx,i-opb = <0x0>; 81 xlnx,i-plb = <0x1>; 82 xlnx,icache-always-used = <0x1>; 83 xlnx,icache-line-len = <0x4>; 84 xlnx,icache-use-fsl = <0x1>; 85 xlnx,ill-opcode-exception = <0x1>; 86 xlnx,instance = "microblaze_0"; 87 xlnx,interconnect = <0x1>; 88 xlnx,interrupt-is-edge = <0x0>; 89 xlnx,iopb-bus-exception = <0x0>; 90 xlnx,mmu-dtlb-size = <0x4>; 91 xlnx,mmu-itlb-size = <0x2>; 92 xlnx,mmu-tlb-access = <0x3>; 93 xlnx,mmu-zones = <0x10>; 94 xlnx,number-of-pc-brk = <0x1>; 95 xlnx,number-of-rd-addr-brk = <0x0>; 96 xlnx,number-of-wr-addr-brk = <0x0>; 97 xlnx,opcode-0x0-illegal = <0x1>; 98 xlnx,pvr = <0x2>; 99 xlnx,pvr-user1 = <0x0>; 100 xlnx,pvr-user2 = <0x0>; 101 xlnx,reset-msr = <0x0>; 102 xlnx,sco = <0x0>; 103 xlnx,unaligned-exceptions = <0x1>; 104 xlnx,use-barrel = <0x1>; 105 xlnx,use-dcache = <0x1>; 106 xlnx,use-div = <0x1>; 107 xlnx,use-ext-brk = <0x1>; 108 xlnx,use-ext-nm-brk = <0x1>; 109 xlnx,use-extended-fsl-instr = <0x0>; 110 xlnx,use-fpu = <0x2>; 111 xlnx,use-hw-mul = <0x2>; 112 xlnx,use-icache = <0x1>; 113 xlnx,use-interrupt = <0x1>; 114 xlnx,use-mmu = <0x3>; 115 xlnx,use-msr-instr = <0x1>; 116 xlnx,use-pcmp-instr = <0x1>; 117 } ; 118 } ; 119 mb_plb: plb@0 { 120 #address-cells = <1>; 121 #size-cells = <1>; 122 compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus"; 123 ranges ; 124 FLASH: flash@a0000000 { 125 bank-width = <2>; 126 compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash"; 127 reg = < 0xa0000000 0x2000000 >; 128 xlnx,family = "virtex5"; 129 xlnx,include-datawidth-matching-0 = <0x1>; 130 xlnx,include-datawidth-matching-1 = <0x0>; 131 xlnx,include-datawidth-matching-2 = <0x0>; 132 xlnx,include-datawidth-matching-3 = <0x0>; 133 xlnx,include-negedge-ioregs = <0x0>; 134 xlnx,include-plb-ipif = <0x1>; 135 xlnx,include-wrbuf = <0x1>; 136 xlnx,max-mem-width = <0x10>; 137 xlnx,mch-native-dwidth = <0x20>; 138 xlnx,mch-plb-clk-period-ps = <0x1f40>; 139 xlnx,mch-splb-awidth = <0x20>; 140 xlnx,mch0-accessbuf-depth = <0x10>; 141 xlnx,mch0-protocol = <0x0>; 142 xlnx,mch0-rddatabuf-depth = <0x10>; 143 xlnx,mch1-accessbuf-depth = <0x10>; 144 xlnx,mch1-protocol = <0x0>; 145 xlnx,mch1-rddatabuf-depth = <0x10>; 146 xlnx,mch2-accessbuf-depth = <0x10>; 147 xlnx,mch2-protocol = <0x0>; 148 xlnx,mch2-rddatabuf-depth = <0x10>; 149 xlnx,mch3-accessbuf-depth = <0x10>; 150 xlnx,mch3-protocol = <0x0>; 151 xlnx,mch3-rddatabuf-depth = <0x10>; 152 xlnx,mem0-width = <0x10>; 153 xlnx,mem1-width = <0x20>; 154 xlnx,mem2-width = <0x20>; 155 xlnx,mem3-width = <0x20>; 156 xlnx,num-banks-mem = <0x1>; 157 xlnx,num-channels = <0x0>; 158 xlnx,priority-mode = <0x0>; 159 xlnx,synch-mem-0 = <0x0>; 160 xlnx,synch-mem-1 = <0x0>; 161 xlnx,synch-mem-2 = <0x0>; 162 xlnx,synch-mem-3 = <0x0>; 163 xlnx,synch-pipedelay-0 = <0x2>; 164 xlnx,synch-pipedelay-1 = <0x2>; 165 xlnx,synch-pipedelay-2 = <0x2>; 166 xlnx,synch-pipedelay-3 = <0x2>; 167 xlnx,tavdv-ps-mem-0 = <0x1adb0>; 168 xlnx,tavdv-ps-mem-1 = <0x3a98>; 169 xlnx,tavdv-ps-mem-2 = <0x3a98>; 170 xlnx,tavdv-ps-mem-3 = <0x3a98>; 171 xlnx,tcedv-ps-mem-0 = <0x1adb0>; 172 xlnx,tcedv-ps-mem-1 = <0x3a98>; 173 xlnx,tcedv-ps-mem-2 = <0x3a98>; 174 xlnx,tcedv-ps-mem-3 = <0x3a98>; 175 xlnx,thzce-ps-mem-0 = <0x88b8>; 176 xlnx,thzce-ps-mem-1 = <0x1b58>; 177 xlnx,thzce-ps-mem-2 = <0x1b58>; 178 xlnx,thzce-ps-mem-3 = <0x1b58>; 179 xlnx,thzoe-ps-mem-0 = <0x1b58>; 180 xlnx,thzoe-ps-mem-1 = <0x1b58>; 181 xlnx,thzoe-ps-mem-2 = <0x1b58>; 182 xlnx,thzoe-ps-mem-3 = <0x1b58>; 183 xlnx,tlzwe-ps-mem-0 = <0x88b8>; 184 xlnx,tlzwe-ps-mem-1 = <0x0>; 185 xlnx,tlzwe-ps-mem-2 = <0x0>; 186 xlnx,tlzwe-ps-mem-3 = <0x0>; 187 xlnx,twc-ps-mem-0 = <0x2af8>; 188 xlnx,twc-ps-mem-1 = <0x3a98>; 189 xlnx,twc-ps-mem-2 = <0x3a98>; 190 xlnx,twc-ps-mem-3 = <0x3a98>; 191 xlnx,twp-ps-mem-0 = <0x11170>; 192 xlnx,twp-ps-mem-1 = <0x2ee0>; 193 xlnx,twp-ps-mem-2 = <0x2ee0>; 194 xlnx,twp-ps-mem-3 = <0x2ee0>; 195 xlnx,xcl0-linesize = <0x4>; 196 xlnx,xcl0-writexfer = <0x1>; 197 xlnx,xcl1-linesize = <0x4>; 198 xlnx,xcl1-writexfer = <0x1>; 199 xlnx,xcl2-linesize = <0x4>; 200 xlnx,xcl2-writexfer = <0x1>; 201 xlnx,xcl3-linesize = <0x4>; 202 xlnx,xcl3-writexfer = <0x1>; 203 } ; 204 Hard_Ethernet_MAC: xps-ll-temac@81c00000 { 205 #address-cells = <1>; 206 #size-cells = <1>; 207 compatible = "xlnx,compound"; 208 ranges ; 209 ethernet@81c00000 { 210 compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a"; 211 interrupt-parent = <&xps_intc_0>; 212 interrupts = < 5 2 >; 213 llink-connected = <&PIM3>; 214 local-mac-address = [ 00 0a 35 00 00 00 ]; 215 reg = < 0x81c00000 0x40 >; 216 xlnx,bus2core-clk-ratio = <0x1>; 217 xlnx,phy-type = <0x1>; 218 xlnx,phyaddr = <0x1>; 219 xlnx,rxcsum = <0x0>; 220 xlnx,rxfifo = <0x1000>; 221 xlnx,temac-type = <0x0>; 222 xlnx,txcsum = <0x0>; 223 xlnx,txfifo = <0x1000>; 224 } ; 225 } ; 226 IIC_EEPROM: i2c@81600000 { 227 compatible = "xlnx,xps-iic-2.00.a"; 228 interrupt-parent = <&xps_intc_0>; 229 interrupts = < 6 2 >; 230 reg = < 0x81600000 0x10000 >; 231 xlnx,clk-freq = <0x7735940>; 232 xlnx,family = "virtex5"; 233 xlnx,gpo-width = <0x1>; 234 xlnx,iic-freq = <0x186a0>; 235 xlnx,scl-inertial-delay = <0x0>; 236 xlnx,sda-inertial-delay = <0x0>; 237 xlnx,ten-bit-adr = <0x0>; 238 } ; 239 LEDs_8Bit: gpio@81400000 { 240 compatible = "xlnx,xps-gpio-1.00.a"; 241 interrupt-parent = <&xps_intc_0>; 242 interrupts = < 7 2 >; 243 reg = < 0x81400000 0x10000 >; 244 xlnx,all-inputs = <0x0>; 245 xlnx,all-inputs-2 = <0x0>; 246 xlnx,dout-default = <0x0>; 247 xlnx,dout-default-2 = <0x0>; 248 xlnx,family = "virtex5"; 249 xlnx,gpio-width = <0x8>; 250 xlnx,interrupt-present = <0x1>; 251 xlnx,is-bidir = <0x1>; 252 xlnx,is-bidir-2 = <0x1>; 253 xlnx,is-dual = <0x0>; 254 xlnx,tri-default = <0xffffffff>; 255 xlnx,tri-default-2 = <0xffffffff>; 256 #gpio-cells = <2>; 257 gpio-controller; 258 } ; 259 260 gpio-leds { 261 compatible = "gpio-leds"; 262 263 heartbeat { 264 label = "Heartbeat"; 265 gpios = <&LEDs_8Bit 4 1>; 266 linux,default-trigger = "heartbeat"; 267 }; 268 269 yellow { 270 label = "Yellow"; 271 gpios = <&LEDs_8Bit 5 1>; 272 }; 273 274 red { 275 label = "Red"; 276 gpios = <&LEDs_8Bit 6 1>; 277 }; 278 279 green { 280 label = "Green"; 281 gpios = <&LEDs_8Bit 7 1>; 282 }; 283 } ; 284 RS232_Uart_1: serial@84000000 { 285 clock-frequency = <125000000>; 286 compatible = "xlnx,xps-uartlite-1.00.a"; 287 current-speed = <115200>; 288 device_type = "serial"; 289 interrupt-parent = <&xps_intc_0>; 290 interrupts = < 8 0 >; 291 port-number = <0>; 292 reg = < 0x84000000 0x10000 >; 293 xlnx,baudrate = <0x1c200>; 294 xlnx,data-bits = <0x8>; 295 xlnx,family = "virtex5"; 296 xlnx,odd-parity = <0x0>; 297 xlnx,use-parity = <0x0>; 298 } ; 299 SysACE_CompactFlash: sysace@83600000 { 300 compatible = "xlnx,xps-sysace-1.00.a"; 301 interrupt-parent = <&xps_intc_0>; 302 interrupts = < 4 2 >; 303 reg = < 0x83600000 0x10000 >; 304 xlnx,family = "virtex5"; 305 xlnx,mem-width = <0x10>; 306 } ; 307 debug_module: debug@84400000 { 308 compatible = "xlnx,mdm-1.00.d"; 309 reg = < 0x84400000 0x10000 >; 310 xlnx,family = "virtex5"; 311 xlnx,interconnect = <0x1>; 312 xlnx,jtag-chain = <0x2>; 313 xlnx,mb-dbg-ports = <0x1>; 314 xlnx,uart-width = <0x8>; 315 xlnx,use-uart = <0x1>; 316 xlnx,write-fsl-ports = <0x0>; 317 } ; 318 mpmc@90000000 { 319 #address-cells = <1>; 320 #size-cells = <1>; 321 compatible = "xlnx,mpmc-4.02.a"; 322 ranges ; 323 PIM3: sdma@84600180 { 324 compatible = "xlnx,ll-dma-1.00.a"; 325 interrupt-parent = <&xps_intc_0>; 326 interrupts = < 2 2 1 2 >; 327 reg = < 0x84600180 0x80 >; 328 } ; 329 } ; 330 xps_intc_0: interrupt-controller@81800000 { 331 #interrupt-cells = <0x2>; 332 compatible = "xlnx,xps-intc-1.00.a"; 333 interrupt-controller ; 334 reg = < 0x81800000 0x10000 >; 335 xlnx,kind-of-intr = <0x100>; 336 xlnx,num-intr-inputs = <0x9>; 337 } ; 338 xps_timer_1: timer@83c00000 { 339 compatible = "xlnx,xps-timer-1.00.a"; 340 interrupt-parent = <&xps_intc_0>; 341 interrupts = < 3 2 >; 342 reg = < 0x83c00000 0x10000 >; 343 xlnx,count-width = <0x20>; 344 xlnx,family = "virtex5"; 345 xlnx,gen0-assert = <0x1>; 346 xlnx,gen1-assert = <0x1>; 347 xlnx,one-timer-only = <0x0>; 348 xlnx,trig0-assert = <0x1>; 349 xlnx,trig1-assert = <0x1>; 350 } ; 351 } ; 352} ; 353