1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Device Tree Generator version: 1.1
4 *
5 * (C) Copyright 2007-2008 Xilinx, Inc.
6 * (C) Copyright 2007-2009 Michal Simek
7 *
8 * Michal SIMEK <monstr@monstr.eu>
9 *
10 * CAUTION: This file is automatically generated by libgen.
11 * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
12 *
13 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
14 */
15
16/dts-v1/;
17/ {
18	#address-cells = <1>;
19	#size-cells = <1>;
20	compatible = "xlnx,microblaze";
21	model = "testing";
22	DDR2_SDRAM: memory@90000000 {
23		device_type = "memory";
24		reg = < 0x90000000 0x10000000 >;
25	} ;
26	aliases {
27		ethernet0 = &Hard_Ethernet_MAC;
28		serial0 = &RS232_Uart_1;
29	} ;
30	chosen {
31		bootargs = "console=ttyUL0,115200 highres=on";
32		stdout-path = "/plb@0/serial@84000000";
33	} ;
34	cpus {
35		#address-cells = <1>;
36		#cpus = <0x1>;
37		#size-cells = <0>;
38		microblaze_0: cpu@0 {
39			clock-frequency = <125000000>;
40			compatible = "xlnx,microblaze-7.10.d";
41			d-cache-baseaddr = <0x90000000>;
42			d-cache-highaddr = <0x9fffffff>;
43			d-cache-line-size = <0x10>;
44			d-cache-size = <0x2000>;
45			device_type = "cpu";
46			i-cache-baseaddr = <0x90000000>;
47			i-cache-highaddr = <0x9fffffff>;
48			i-cache-line-size = <0x10>;
49			i-cache-size = <0x2000>;
50			model = "microblaze,7.10.d";
51			reg = <0>;
52			timebase-frequency = <125000000>;
53			xlnx,addr-tag-bits = <0xf>;
54			xlnx,allow-dcache-wr = <0x1>;
55			xlnx,allow-icache-wr = <0x1>;
56			xlnx,area-optimized = <0x0>;
57			xlnx,cache-byte-size = <0x2000>;
58			xlnx,d-lmb = <0x1>;
59			xlnx,d-opb = <0x0>;
60			xlnx,d-plb = <0x1>;
61			xlnx,data-size = <0x20>;
62			xlnx,dcache-addr-tag = <0xf>;
63			xlnx,dcache-always-used = <0x1>;
64			xlnx,dcache-byte-size = <0x2000>;
65			xlnx,dcache-line-len = <0x4>;
66			xlnx,dcache-use-fsl = <0x1>;
67			xlnx,debug-enabled = <0x1>;
68			xlnx,div-zero-exception = <0x1>;
69			xlnx,dopb-bus-exception = <0x0>;
70			xlnx,dynamic-bus-sizing = <0x1>;
71			xlnx,edge-is-positive = <0x1>;
72			xlnx,family = "virtex5";
73			xlnx,endianness = <0x1>;
74			xlnx,fpu-exception = <0x1>;
75			xlnx,fsl-data-size = <0x20>;
76			xlnx,fsl-exception = <0x0>;
77			xlnx,fsl-links = <0x0>;
78			xlnx,i-lmb = <0x1>;
79			xlnx,i-opb = <0x0>;
80			xlnx,i-plb = <0x1>;
81			xlnx,icache-always-used = <0x1>;
82			xlnx,icache-line-len = <0x4>;
83			xlnx,icache-use-fsl = <0x1>;
84			xlnx,ill-opcode-exception = <0x1>;
85			xlnx,instance = "microblaze_0";
86			xlnx,interconnect = <0x1>;
87			xlnx,interrupt-is-edge = <0x0>;
88			xlnx,iopb-bus-exception = <0x0>;
89			xlnx,mmu-dtlb-size = <0x4>;
90			xlnx,mmu-itlb-size = <0x2>;
91			xlnx,mmu-tlb-access = <0x3>;
92			xlnx,mmu-zones = <0x10>;
93			xlnx,number-of-pc-brk = <0x1>;
94			xlnx,number-of-rd-addr-brk = <0x0>;
95			xlnx,number-of-wr-addr-brk = <0x0>;
96			xlnx,opcode-0x0-illegal = <0x1>;
97			xlnx,pvr = <0x2>;
98			xlnx,pvr-user1 = <0x0>;
99			xlnx,pvr-user2 = <0x0>;
100			xlnx,reset-msr = <0x0>;
101			xlnx,sco = <0x0>;
102			xlnx,unaligned-exceptions = <0x1>;
103			xlnx,use-barrel = <0x1>;
104			xlnx,use-dcache = <0x1>;
105			xlnx,use-div = <0x1>;
106			xlnx,use-ext-brk = <0x1>;
107			xlnx,use-ext-nm-brk = <0x1>;
108			xlnx,use-extended-fsl-instr = <0x0>;
109			xlnx,use-fpu = <0x2>;
110			xlnx,use-hw-mul = <0x2>;
111			xlnx,use-icache = <0x1>;
112			xlnx,use-interrupt = <0x1>;
113			xlnx,use-mmu = <0x3>;
114			xlnx,use-msr-instr = <0x1>;
115			xlnx,use-pcmp-instr = <0x1>;
116		} ;
117	} ;
118	mb_plb: plb@0 {
119		#address-cells = <1>;
120		#size-cells = <1>;
121		compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus";
122		ranges ;
123		FLASH: flash@a0000000 {
124			bank-width = <2>;
125			compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
126			reg = < 0xa0000000 0x2000000 >;
127			xlnx,family = "virtex5";
128			xlnx,include-datawidth-matching-0 = <0x1>;
129			xlnx,include-datawidth-matching-1 = <0x0>;
130			xlnx,include-datawidth-matching-2 = <0x0>;
131			xlnx,include-datawidth-matching-3 = <0x0>;
132			xlnx,include-negedge-ioregs = <0x0>;
133			xlnx,include-plb-ipif = <0x1>;
134			xlnx,include-wrbuf = <0x1>;
135			xlnx,max-mem-width = <0x10>;
136			xlnx,mch-native-dwidth = <0x20>;
137			xlnx,mch-plb-clk-period-ps = <0x1f40>;
138			xlnx,mch-splb-awidth = <0x20>;
139			xlnx,mch0-accessbuf-depth = <0x10>;
140			xlnx,mch0-protocol = <0x0>;
141			xlnx,mch0-rddatabuf-depth = <0x10>;
142			xlnx,mch1-accessbuf-depth = <0x10>;
143			xlnx,mch1-protocol = <0x0>;
144			xlnx,mch1-rddatabuf-depth = <0x10>;
145			xlnx,mch2-accessbuf-depth = <0x10>;
146			xlnx,mch2-protocol = <0x0>;
147			xlnx,mch2-rddatabuf-depth = <0x10>;
148			xlnx,mch3-accessbuf-depth = <0x10>;
149			xlnx,mch3-protocol = <0x0>;
150			xlnx,mch3-rddatabuf-depth = <0x10>;
151			xlnx,mem0-width = <0x10>;
152			xlnx,mem1-width = <0x20>;
153			xlnx,mem2-width = <0x20>;
154			xlnx,mem3-width = <0x20>;
155			xlnx,num-banks-mem = <0x1>;
156			xlnx,num-channels = <0x0>;
157			xlnx,priority-mode = <0x0>;
158			xlnx,synch-mem-0 = <0x0>;
159			xlnx,synch-mem-1 = <0x0>;
160			xlnx,synch-mem-2 = <0x0>;
161			xlnx,synch-mem-3 = <0x0>;
162			xlnx,synch-pipedelay-0 = <0x2>;
163			xlnx,synch-pipedelay-1 = <0x2>;
164			xlnx,synch-pipedelay-2 = <0x2>;
165			xlnx,synch-pipedelay-3 = <0x2>;
166			xlnx,tavdv-ps-mem-0 = <0x1adb0>;
167			xlnx,tavdv-ps-mem-1 = <0x3a98>;
168			xlnx,tavdv-ps-mem-2 = <0x3a98>;
169			xlnx,tavdv-ps-mem-3 = <0x3a98>;
170			xlnx,tcedv-ps-mem-0 = <0x1adb0>;
171			xlnx,tcedv-ps-mem-1 = <0x3a98>;
172			xlnx,tcedv-ps-mem-2 = <0x3a98>;
173			xlnx,tcedv-ps-mem-3 = <0x3a98>;
174			xlnx,thzce-ps-mem-0 = <0x88b8>;
175			xlnx,thzce-ps-mem-1 = <0x1b58>;
176			xlnx,thzce-ps-mem-2 = <0x1b58>;
177			xlnx,thzce-ps-mem-3 = <0x1b58>;
178			xlnx,thzoe-ps-mem-0 = <0x1b58>;
179			xlnx,thzoe-ps-mem-1 = <0x1b58>;
180			xlnx,thzoe-ps-mem-2 = <0x1b58>;
181			xlnx,thzoe-ps-mem-3 = <0x1b58>;
182			xlnx,tlzwe-ps-mem-0 = <0x88b8>;
183			xlnx,tlzwe-ps-mem-1 = <0x0>;
184			xlnx,tlzwe-ps-mem-2 = <0x0>;
185			xlnx,tlzwe-ps-mem-3 = <0x0>;
186			xlnx,twc-ps-mem-0 = <0x2af8>;
187			xlnx,twc-ps-mem-1 = <0x3a98>;
188			xlnx,twc-ps-mem-2 = <0x3a98>;
189			xlnx,twc-ps-mem-3 = <0x3a98>;
190			xlnx,twp-ps-mem-0 = <0x11170>;
191			xlnx,twp-ps-mem-1 = <0x2ee0>;
192			xlnx,twp-ps-mem-2 = <0x2ee0>;
193			xlnx,twp-ps-mem-3 = <0x2ee0>;
194			xlnx,xcl0-linesize = <0x4>;
195			xlnx,xcl0-writexfer = <0x1>;
196			xlnx,xcl1-linesize = <0x4>;
197			xlnx,xcl1-writexfer = <0x1>;
198			xlnx,xcl2-linesize = <0x4>;
199			xlnx,xcl2-writexfer = <0x1>;
200			xlnx,xcl3-linesize = <0x4>;
201			xlnx,xcl3-writexfer = <0x1>;
202		} ;
203		Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
204			#address-cells = <1>;
205			#size-cells = <1>;
206			compatible = "xlnx,compound";
207			ranges ;
208			ethernet@81c00000 {
209				compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a";
210				interrupt-parent = <&xps_intc_0>;
211				interrupts = < 5 2 >;
212				llink-connected = <&PIM3>;
213				local-mac-address = [ 00 0a 35 00 00 00 ];
214				reg = < 0x81c00000 0x40 >;
215				xlnx,bus2core-clk-ratio = <0x1>;
216				xlnx,phy-type = <0x1>;
217				xlnx,phyaddr = <0x1>;
218				xlnx,rxcsum = <0x0>;
219				xlnx,rxfifo = <0x1000>;
220				xlnx,temac-type = <0x0>;
221				xlnx,txcsum = <0x0>;
222				xlnx,txfifo = <0x1000>;
223			} ;
224		} ;
225		IIC_EEPROM: i2c@81600000 {
226			compatible = "xlnx,xps-iic-2.00.a";
227			interrupt-parent = <&xps_intc_0>;
228			interrupts = < 6 2 >;
229			reg = < 0x81600000 0x10000 >;
230			xlnx,clk-freq = <0x7735940>;
231			xlnx,family = "virtex5";
232			xlnx,gpo-width = <0x1>;
233			xlnx,iic-freq = <0x186a0>;
234			xlnx,scl-inertial-delay = <0x0>;
235			xlnx,sda-inertial-delay = <0x0>;
236			xlnx,ten-bit-adr = <0x0>;
237		} ;
238		LEDs_8Bit: gpio@81400000 {
239			compatible = "xlnx,xps-gpio-1.00.a";
240			interrupt-parent = <&xps_intc_0>;
241			interrupts = < 7 2 >;
242			reg = < 0x81400000 0x10000 >;
243			xlnx,all-inputs = <0x0>;
244			xlnx,all-inputs-2 = <0x0>;
245			xlnx,dout-default = <0x0>;
246			xlnx,dout-default-2 = <0x0>;
247			xlnx,family = "virtex5";
248			xlnx,gpio-width = <0x8>;
249			xlnx,interrupt-present = <0x1>;
250			xlnx,is-bidir = <0x1>;
251			xlnx,is-bidir-2 = <0x1>;
252			xlnx,is-dual = <0x0>;
253			xlnx,tri-default = <0xffffffff>;
254			xlnx,tri-default-2 = <0xffffffff>;
255			#gpio-cells = <2>;
256			gpio-controller;
257		} ;
258
259		gpio-leds {
260			compatible = "gpio-leds";
261
262			heartbeat {
263				label = "Heartbeat";
264				gpios = <&LEDs_8Bit 4 1>;
265				linux,default-trigger = "heartbeat";
266			};
267
268			yellow {
269				label = "Yellow";
270				gpios = <&LEDs_8Bit 5 1>;
271			};
272
273			red {
274				label = "Red";
275				gpios = <&LEDs_8Bit 6 1>;
276			};
277
278			green {
279				label = "Green";
280				gpios = <&LEDs_8Bit 7 1>;
281			};
282		} ;
283
284		gpio-restart {
285			compatible = "gpio-restart";
286			/*
287			 * FIXME: is this active low or active high?
288			 * the current flag (1) indicates active low.
289			 * delay measures are templates, should be adjusted
290			 * to datasheet or trial-and-error with real hardware.
291			 */
292			gpios = <&LEDs_8Bit 2 1>;
293			active-delay = <100>;
294			inactive-delay = <10>;
295			wait-delay = <100>;
296		};
297
298		RS232_Uart_1: serial@84000000 {
299			clock-frequency = <125000000>;
300			compatible = "xlnx,xps-uartlite-1.00.a";
301			current-speed = <115200>;
302			device_type = "serial";
303			interrupt-parent = <&xps_intc_0>;
304			interrupts = < 8 0 >;
305			port-number = <0>;
306			reg = < 0x84000000 0x10000 >;
307			xlnx,baudrate = <0x1c200>;
308			xlnx,data-bits = <0x8>;
309			xlnx,family = "virtex5";
310			xlnx,odd-parity = <0x0>;
311			xlnx,use-parity = <0x0>;
312		} ;
313		debug_module: debug@84400000 {
314			compatible = "xlnx,mdm-1.00.d";
315			reg = < 0x84400000 0x10000 >;
316			xlnx,family = "virtex5";
317			xlnx,interconnect = <0x1>;
318			xlnx,jtag-chain = <0x2>;
319			xlnx,mb-dbg-ports = <0x1>;
320			xlnx,uart-width = <0x8>;
321			xlnx,use-uart = <0x1>;
322			xlnx,write-fsl-ports = <0x0>;
323		} ;
324		mpmc@90000000 {
325			#address-cells = <1>;
326			#size-cells = <1>;
327			compatible = "xlnx,mpmc-4.02.a";
328			ranges ;
329			PIM3: sdma@84600180 {
330				compatible = "xlnx,ll-dma-1.00.a";
331				interrupt-parent = <&xps_intc_0>;
332				interrupts = < 2 2 1 2 >;
333				reg = < 0x84600180 0x80 >;
334			} ;
335		} ;
336		xps_intc_0: interrupt-controller@81800000 {
337			#interrupt-cells = <0x2>;
338			compatible = "xlnx,xps-intc-1.00.a";
339			interrupt-controller ;
340			reg = < 0x81800000 0x10000 >;
341			xlnx,kind-of-intr = <0x100>;
342			xlnx,num-intr-inputs = <0x9>;
343		} ;
344		xps_timer_1: timer@83c00000 {
345			compatible = "xlnx,xps-timer-1.00.a";
346			interrupt-parent = <&xps_intc_0>;
347			interrupts = < 3 2 >;
348			reg = < 0x83c00000 0x10000 >;
349			xlnx,count-width = <0x20>;
350			xlnx,family = "virtex5";
351			xlnx,gen0-assert = <0x1>;
352			xlnx,gen1-assert = <0x1>;
353			xlnx,one-timer-only = <0x0>;
354			xlnx,trig0-assert = <0x1>;
355			xlnx,trig1-assert = <0x1>;
356		} ;
357	} ;
358}  ;
359