1 /* 2 * arch/m68k/q40/config.c 3 * 4 * Copyright (C) 1999 Richard Zidlicky 5 * 6 * originally based on: 7 * 8 * linux/bvme/config.c 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file README.legal in the main directory of this archive 12 * for more details. 13 */ 14 15 #include <linux/errno.h> 16 #include <linux/types.h> 17 #include <linux/kernel.h> 18 #include <linux/mm.h> 19 #include <linux/tty.h> 20 #include <linux/console.h> 21 #include <linux/linkage.h> 22 #include <linux/init.h> 23 #include <linux/major.h> 24 #include <linux/serial_reg.h> 25 #include <linux/rtc.h> 26 #include <linux/vt_kern.h> 27 #include <linux/bcd.h> 28 #include <linux/platform_device.h> 29 30 #include <asm/io.h> 31 #include <asm/bootinfo.h> 32 #include <asm/setup.h> 33 #include <asm/irq.h> 34 #include <asm/traps.h> 35 #include <asm/machdep.h> 36 #include <asm/q40_master.h> 37 #include <asm/config.h> 38 39 extern void q40_init_IRQ(void); 40 static void q40_get_model(char *model); 41 extern void q40_sched_init(void); 42 43 static int q40_hwclk(int, struct rtc_time *); 44 static unsigned int q40_get_ss(void); 45 static int q40_get_rtc_pll(struct rtc_pll_info *pll); 46 static int q40_set_rtc_pll(struct rtc_pll_info *pll); 47 48 extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/); 49 50 static void q40_mem_console_write(struct console *co, const char *b, 51 unsigned int count); 52 53 extern int ql_ticks; 54 55 static struct console q40_console_driver = { 56 .name = "debug", 57 .write = q40_mem_console_write, 58 .flags = CON_PRINTBUFFER, 59 .index = -1, 60 }; 61 62 63 /* early debugging function:*/ 64 extern char *q40_mem_cptr; /*=(char *)0xff020000;*/ 65 static int _cpleft; 66 67 static void q40_mem_console_write(struct console *co, const char *s, 68 unsigned int count) 69 { 70 const char *p = s; 71 72 if (count < _cpleft) { 73 while (count-- > 0) { 74 *q40_mem_cptr = *p++; 75 q40_mem_cptr += 4; 76 _cpleft--; 77 } 78 } 79 } 80 81 static int __init q40_debug_setup(char *arg) 82 { 83 /* useful for early debugging stages - writes kernel messages into SRAM */ 84 if (MACH_IS_Q40 && !strncmp(arg, "mem", 3)) { 85 /*pr_info("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/ 86 _cpleft = 2000 - ((long)q40_mem_cptr-0xff020000) / 4; 87 register_console(&q40_console_driver); 88 } 89 return 0; 90 } 91 92 early_param("debug", q40_debug_setup); 93 94 #if 0 95 void printq40(char *str) 96 { 97 int l = strlen(str); 98 char *p = q40_mem_cptr; 99 100 while (l-- > 0 && _cpleft-- > 0) { 101 *p = *str++; 102 p += 4; 103 } 104 q40_mem_cptr = p; 105 } 106 #endif 107 108 static int halted; 109 110 #ifdef CONFIG_HEARTBEAT 111 static void q40_heartbeat(int on) 112 { 113 if (halted) 114 return; 115 116 if (on) 117 Q40_LED_ON(); 118 else 119 Q40_LED_OFF(); 120 } 121 #endif 122 123 static void q40_reset(void) 124 { 125 halted = 1; 126 pr_info("*******************************************\n" 127 "Called q40_reset : press the RESET button!!\n" 128 "*******************************************\n"); 129 Q40_LED_ON(); 130 while (1) 131 ; 132 } 133 134 static void q40_halt(void) 135 { 136 halted = 1; 137 pr_info("*******************\n" 138 " Called q40_halt\n" 139 "*******************\n"); 140 Q40_LED_ON(); 141 while (1) 142 ; 143 } 144 145 static void q40_get_model(char *model) 146 { 147 sprintf(model, "Q40"); 148 } 149 150 static unsigned int serports[] = 151 { 152 0x3f8,0x2f8,0x3e8,0x2e8,0 153 }; 154 155 static void __init q40_disable_irqs(void) 156 { 157 unsigned i, j; 158 159 j = 0; 160 while ((i = serports[j++])) 161 outb(0, i + UART_IER); 162 master_outb(0, EXT_ENABLE_REG); 163 master_outb(0, KEY_IRQ_ENABLE_REG); 164 } 165 166 void __init config_q40(void) 167 { 168 mach_sched_init = q40_sched_init; 169 170 mach_init_IRQ = q40_init_IRQ; 171 mach_hwclk = q40_hwclk; 172 mach_get_ss = q40_get_ss; 173 mach_get_rtc_pll = q40_get_rtc_pll; 174 mach_set_rtc_pll = q40_set_rtc_pll; 175 176 mach_reset = q40_reset; 177 mach_get_model = q40_get_model; 178 179 #if IS_ENABLED(CONFIG_INPUT_M68K_BEEP) 180 mach_beep = q40_mksound; 181 #endif 182 #ifdef CONFIG_HEARTBEAT 183 mach_heartbeat = q40_heartbeat; 184 #endif 185 mach_halt = q40_halt; 186 187 /* disable a few things that SMSQ might have left enabled */ 188 q40_disable_irqs(); 189 } 190 191 192 int __init q40_parse_bootinfo(const struct bi_record *rec) 193 { 194 return 1; 195 } 196 197 /* 198 * Looks like op is non-zero for setting the clock, and zero for 199 * reading the clock. 200 * 201 * struct hwclk_time { 202 * unsigned sec; 0..59 203 * unsigned min; 0..59 204 * unsigned hour; 0..23 205 * unsigned day; 1..31 206 * unsigned mon; 0..11 207 * unsigned year; 00... 208 * int wday; 0..6, 0 is Sunday, -1 means unknown/don't set 209 * }; 210 */ 211 212 static int q40_hwclk(int op, struct rtc_time *t) 213 { 214 if (op) { 215 /* Write.... */ 216 Q40_RTC_CTRL |= Q40_RTC_WRITE; 217 218 Q40_RTC_SECS = bin2bcd(t->tm_sec); 219 Q40_RTC_MINS = bin2bcd(t->tm_min); 220 Q40_RTC_HOUR = bin2bcd(t->tm_hour); 221 Q40_RTC_DATE = bin2bcd(t->tm_mday); 222 Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1); 223 Q40_RTC_YEAR = bin2bcd(t->tm_year%100); 224 if (t->tm_wday >= 0) 225 Q40_RTC_DOW = bin2bcd(t->tm_wday+1); 226 227 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE); 228 } else { 229 /* Read.... */ 230 Q40_RTC_CTRL |= Q40_RTC_READ; 231 232 t->tm_year = bcd2bin (Q40_RTC_YEAR); 233 t->tm_mon = bcd2bin (Q40_RTC_MNTH)-1; 234 t->tm_mday = bcd2bin (Q40_RTC_DATE); 235 t->tm_hour = bcd2bin (Q40_RTC_HOUR); 236 t->tm_min = bcd2bin (Q40_RTC_MINS); 237 t->tm_sec = bcd2bin (Q40_RTC_SECS); 238 239 Q40_RTC_CTRL &= ~(Q40_RTC_READ); 240 241 if (t->tm_year < 70) 242 t->tm_year += 100; 243 t->tm_wday = bcd2bin(Q40_RTC_DOW)-1; 244 } 245 246 return 0; 247 } 248 249 static unsigned int q40_get_ss(void) 250 { 251 return bcd2bin(Q40_RTC_SECS); 252 } 253 254 /* get and set PLL calibration of RTC clock */ 255 #define Q40_RTC_PLL_MASK ((1<<5)-1) 256 #define Q40_RTC_PLL_SIGN (1<<5) 257 258 static int q40_get_rtc_pll(struct rtc_pll_info *pll) 259 { 260 int tmp = Q40_RTC_CTRL; 261 262 pll->pll_ctrl = 0; 263 pll->pll_value = tmp & Q40_RTC_PLL_MASK; 264 if (tmp & Q40_RTC_PLL_SIGN) 265 pll->pll_value = -pll->pll_value; 266 pll->pll_max = 31; 267 pll->pll_min = -31; 268 pll->pll_posmult = 512; 269 pll->pll_negmult = 256; 270 pll->pll_clock = 125829120; 271 272 return 0; 273 } 274 275 static int q40_set_rtc_pll(struct rtc_pll_info *pll) 276 { 277 if (!pll->pll_ctrl) { 278 /* the docs are a bit unclear so I am doublesetting */ 279 /* RTC_WRITE here ... */ 280 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) | 281 Q40_RTC_WRITE; 282 Q40_RTC_CTRL |= Q40_RTC_WRITE; 283 Q40_RTC_CTRL = tmp; 284 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE); 285 return 0; 286 } else 287 return -EINVAL; 288 } 289 290 #define PCIDE_BASE1 0x1f0 291 #define PCIDE_BASE2 0x170 292 #define PCIDE_CTL 0x206 293 294 static const struct resource q40_pata_rsrc_0[] __initconst = { 295 DEFINE_RES_MEM(q40_isa_io_base + PCIDE_BASE1 * 4, 0x38), 296 DEFINE_RES_MEM(q40_isa_io_base + (PCIDE_BASE1 + PCIDE_CTL) * 4, 2), 297 DEFINE_RES_IO(PCIDE_BASE1, 8), 298 DEFINE_RES_IO(PCIDE_BASE1 + PCIDE_CTL, 1), 299 DEFINE_RES_IRQ(14), 300 }; 301 302 static const struct resource q40_pata_rsrc_1[] __initconst = { 303 DEFINE_RES_MEM(q40_isa_io_base + PCIDE_BASE2 * 4, 0x38), 304 DEFINE_RES_MEM(q40_isa_io_base + (PCIDE_BASE2 + PCIDE_CTL) * 4, 2), 305 DEFINE_RES_IO(PCIDE_BASE2, 8), 306 DEFINE_RES_IO(PCIDE_BASE2 + PCIDE_CTL, 1), 307 DEFINE_RES_IRQ(15), 308 }; 309 310 static __init int q40_platform_init(void) 311 { 312 if (!MACH_IS_Q40) 313 return -ENODEV; 314 315 platform_device_register_simple("q40kbd", -1, NULL, 0); 316 317 platform_device_register_simple("atari-falcon-ide", 0, q40_pata_rsrc_0, 318 ARRAY_SIZE(q40_pata_rsrc_0)); 319 320 platform_device_register_simple("atari-falcon-ide", 1, q40_pata_rsrc_1, 321 ARRAY_SIZE(q40_pata_rsrc_1)); 322 323 return 0; 324 } 325 arch_initcall(q40_platform_init); 326