1 /* 2 * arch/m68k/q40/config.c 3 * 4 * Copyright (C) 1999 Richard Zidlicky 5 * 6 * originally based on: 7 * 8 * linux/bvme/config.c 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file README.legal in the main directory of this archive 12 * for more details. 13 */ 14 15 #include <linux/errno.h> 16 #include <linux/types.h> 17 #include <linux/kernel.h> 18 #include <linux/mm.h> 19 #include <linux/tty.h> 20 #include <linux/console.h> 21 #include <linux/linkage.h> 22 #include <linux/init.h> 23 #include <linux/major.h> 24 #include <linux/serial_reg.h> 25 #include <linux/rtc.h> 26 #include <linux/vt_kern.h> 27 #include <linux/bcd.h> 28 #include <linux/platform_device.h> 29 30 #include <asm/io.h> 31 #include <asm/bootinfo.h> 32 #include <asm/pgtable.h> 33 #include <asm/setup.h> 34 #include <asm/irq.h> 35 #include <asm/traps.h> 36 #include <asm/machdep.h> 37 #include <asm/q40_master.h> 38 39 extern void q40_init_IRQ(void); 40 static void q40_get_model(char *model); 41 extern void q40_sched_init(irq_handler_t handler); 42 43 static u32 q40_gettimeoffset(void); 44 static int q40_hwclk(int, struct rtc_time *); 45 static unsigned int q40_get_ss(void); 46 static int q40_get_rtc_pll(struct rtc_pll_info *pll); 47 static int q40_set_rtc_pll(struct rtc_pll_info *pll); 48 49 extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/); 50 51 static void q40_mem_console_write(struct console *co, const char *b, 52 unsigned int count); 53 54 extern int ql_ticks; 55 56 static struct console q40_console_driver = { 57 .name = "debug", 58 .write = q40_mem_console_write, 59 .flags = CON_PRINTBUFFER, 60 .index = -1, 61 }; 62 63 64 /* early debugging function:*/ 65 extern char *q40_mem_cptr; /*=(char *)0xff020000;*/ 66 static int _cpleft; 67 68 static void q40_mem_console_write(struct console *co, const char *s, 69 unsigned int count) 70 { 71 const char *p = s; 72 73 if (count < _cpleft) { 74 while (count-- > 0) { 75 *q40_mem_cptr = *p++; 76 q40_mem_cptr += 4; 77 _cpleft--; 78 } 79 } 80 } 81 82 static int __init q40_debug_setup(char *arg) 83 { 84 /* useful for early debugging stages - writes kernel messages into SRAM */ 85 if (MACH_IS_Q40 && !strncmp(arg, "mem", 3)) { 86 /*pr_info("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/ 87 _cpleft = 2000 - ((long)q40_mem_cptr-0xff020000) / 4; 88 register_console(&q40_console_driver); 89 } 90 return 0; 91 } 92 93 early_param("debug", q40_debug_setup); 94 95 #if 0 96 void printq40(char *str) 97 { 98 int l = strlen(str); 99 char *p = q40_mem_cptr; 100 101 while (l-- > 0 && _cpleft-- > 0) { 102 *p = *str++; 103 p += 4; 104 } 105 q40_mem_cptr = p; 106 } 107 #endif 108 109 static int halted; 110 111 #ifdef CONFIG_HEARTBEAT 112 static void q40_heartbeat(int on) 113 { 114 if (halted) 115 return; 116 117 if (on) 118 Q40_LED_ON(); 119 else 120 Q40_LED_OFF(); 121 } 122 #endif 123 124 static void q40_reset(void) 125 { 126 halted = 1; 127 pr_info("*******************************************\n" 128 "Called q40_reset : press the RESET button!!\n" 129 "*******************************************\n"); 130 Q40_LED_ON(); 131 while (1) 132 ; 133 } 134 135 static void q40_halt(void) 136 { 137 halted = 1; 138 pr_info("*******************\n" 139 " Called q40_halt\n" 140 "*******************\n"); 141 Q40_LED_ON(); 142 while (1) 143 ; 144 } 145 146 static void q40_get_model(char *model) 147 { 148 sprintf(model, "Q40"); 149 } 150 151 static unsigned int serports[] = 152 { 153 0x3f8,0x2f8,0x3e8,0x2e8,0 154 }; 155 156 static void __init q40_disable_irqs(void) 157 { 158 unsigned i, j; 159 160 j = 0; 161 while ((i = serports[j++])) 162 outb(0, i + UART_IER); 163 master_outb(0, EXT_ENABLE_REG); 164 master_outb(0, KEY_IRQ_ENABLE_REG); 165 } 166 167 void __init config_q40(void) 168 { 169 mach_sched_init = q40_sched_init; 170 171 mach_init_IRQ = q40_init_IRQ; 172 arch_gettimeoffset = q40_gettimeoffset; 173 mach_hwclk = q40_hwclk; 174 mach_get_ss = q40_get_ss; 175 mach_get_rtc_pll = q40_get_rtc_pll; 176 mach_set_rtc_pll = q40_set_rtc_pll; 177 178 mach_reset = q40_reset; 179 mach_get_model = q40_get_model; 180 181 #if IS_ENABLED(CONFIG_INPUT_M68K_BEEP) 182 mach_beep = q40_mksound; 183 #endif 184 #ifdef CONFIG_HEARTBEAT 185 mach_heartbeat = q40_heartbeat; 186 #endif 187 mach_halt = q40_halt; 188 189 /* disable a few things that SMSQ might have left enabled */ 190 q40_disable_irqs(); 191 192 /* no DMA at all, but ide-scsi requires it.. make sure 193 * all physical RAM fits into the boundary - otherwise 194 * allocator may play costly and useless tricks */ 195 mach_max_dma_address = 1024*1024*1024; 196 } 197 198 199 int __init q40_parse_bootinfo(const struct bi_record *rec) 200 { 201 return 1; 202 } 203 204 205 static u32 q40_gettimeoffset(void) 206 { 207 return 5000 * (ql_ticks != 0) * 1000; 208 } 209 210 211 /* 212 * Looks like op is non-zero for setting the clock, and zero for 213 * reading the clock. 214 * 215 * struct hwclk_time { 216 * unsigned sec; 0..59 217 * unsigned min; 0..59 218 * unsigned hour; 0..23 219 * unsigned day; 1..31 220 * unsigned mon; 0..11 221 * unsigned year; 00... 222 * int wday; 0..6, 0 is Sunday, -1 means unknown/don't set 223 * }; 224 */ 225 226 static int q40_hwclk(int op, struct rtc_time *t) 227 { 228 if (op) { 229 /* Write.... */ 230 Q40_RTC_CTRL |= Q40_RTC_WRITE; 231 232 Q40_RTC_SECS = bin2bcd(t->tm_sec); 233 Q40_RTC_MINS = bin2bcd(t->tm_min); 234 Q40_RTC_HOUR = bin2bcd(t->tm_hour); 235 Q40_RTC_DATE = bin2bcd(t->tm_mday); 236 Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1); 237 Q40_RTC_YEAR = bin2bcd(t->tm_year%100); 238 if (t->tm_wday >= 0) 239 Q40_RTC_DOW = bin2bcd(t->tm_wday+1); 240 241 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE); 242 } else { 243 /* Read.... */ 244 Q40_RTC_CTRL |= Q40_RTC_READ; 245 246 t->tm_year = bcd2bin (Q40_RTC_YEAR); 247 t->tm_mon = bcd2bin (Q40_RTC_MNTH)-1; 248 t->tm_mday = bcd2bin (Q40_RTC_DATE); 249 t->tm_hour = bcd2bin (Q40_RTC_HOUR); 250 t->tm_min = bcd2bin (Q40_RTC_MINS); 251 t->tm_sec = bcd2bin (Q40_RTC_SECS); 252 253 Q40_RTC_CTRL &= ~(Q40_RTC_READ); 254 255 if (t->tm_year < 70) 256 t->tm_year += 100; 257 t->tm_wday = bcd2bin(Q40_RTC_DOW)-1; 258 } 259 260 return 0; 261 } 262 263 static unsigned int q40_get_ss(void) 264 { 265 return bcd2bin(Q40_RTC_SECS); 266 } 267 268 /* get and set PLL calibration of RTC clock */ 269 #define Q40_RTC_PLL_MASK ((1<<5)-1) 270 #define Q40_RTC_PLL_SIGN (1<<5) 271 272 static int q40_get_rtc_pll(struct rtc_pll_info *pll) 273 { 274 int tmp = Q40_RTC_CTRL; 275 276 pll->pll_value = tmp & Q40_RTC_PLL_MASK; 277 if (tmp & Q40_RTC_PLL_SIGN) 278 pll->pll_value = -pll->pll_value; 279 pll->pll_max = 31; 280 pll->pll_min = -31; 281 pll->pll_posmult = 512; 282 pll->pll_negmult = 256; 283 pll->pll_clock = 125829120; 284 285 return 0; 286 } 287 288 static int q40_set_rtc_pll(struct rtc_pll_info *pll) 289 { 290 if (!pll->pll_ctrl) { 291 /* the docs are a bit unclear so I am doublesetting */ 292 /* RTC_WRITE here ... */ 293 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) | 294 Q40_RTC_WRITE; 295 Q40_RTC_CTRL |= Q40_RTC_WRITE; 296 Q40_RTC_CTRL = tmp; 297 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE); 298 return 0; 299 } else 300 return -EINVAL; 301 } 302 303 static __init int q40_add_kbd_device(void) 304 { 305 struct platform_device *pdev; 306 307 if (!MACH_IS_Q40) 308 return -ENODEV; 309 310 pdev = platform_device_register_simple("q40kbd", -1, NULL, 0); 311 return PTR_ERR_OR_ZERO(pdev); 312 } 313 arch_initcall(q40_add_kbd_device); 314