1 /* 2 * arch/m68k/q40/config.c 3 * 4 * Copyright (C) 1999 Richard Zidlicky 5 * 6 * originally based on: 7 * 8 * linux/bvme/config.c 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file README.legal in the main directory of this archive 12 * for more details. 13 */ 14 15 #include <linux/types.h> 16 #include <linux/kernel.h> 17 #include <linux/mm.h> 18 #include <linux/tty.h> 19 #include <linux/console.h> 20 #include <linux/linkage.h> 21 #include <linux/init.h> 22 #include <linux/major.h> 23 #include <linux/serial_reg.h> 24 #include <linux/rtc.h> 25 #include <linux/vt_kern.h> 26 #include <linux/bcd.h> 27 28 #include <asm/io.h> 29 #include <asm/rtc.h> 30 #include <asm/bootinfo.h> 31 #include <asm/system.h> 32 #include <asm/pgtable.h> 33 #include <asm/setup.h> 34 #include <asm/irq.h> 35 #include <asm/traps.h> 36 #include <asm/machdep.h> 37 #include <asm/q40_master.h> 38 39 extern irqreturn_t q40_process_int(int level, struct pt_regs *regs); 40 extern void q40_init_IRQ(void); 41 static void q40_get_model(char *model); 42 extern void q40_sched_init(irq_handler_t handler); 43 44 static unsigned long q40_gettimeoffset(void); 45 static int q40_hwclk(int, struct rtc_time *); 46 static unsigned int q40_get_ss(void); 47 static int q40_set_clock_mmss(unsigned long); 48 static int q40_get_rtc_pll(struct rtc_pll_info *pll); 49 static int q40_set_rtc_pll(struct rtc_pll_info *pll); 50 extern void q40_waitbut(void); 51 void q40_set_vectors(void); 52 53 extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/); 54 55 static void q40_mem_console_write(struct console *co, const char *b, 56 unsigned int count); 57 58 extern int ql_ticks; 59 60 static struct console q40_console_driver = { 61 .name = "debug", 62 .write = q40_mem_console_write, 63 .flags = CON_PRINTBUFFER, 64 .index = -1, 65 }; 66 67 68 /* early debugging function:*/ 69 extern char *q40_mem_cptr; /*=(char *)0xff020000;*/ 70 static int _cpleft; 71 72 static void q40_mem_console_write(struct console *co, const char *s, 73 unsigned int count) 74 { 75 const char *p = s; 76 77 if (count < _cpleft) { 78 while (count-- > 0) { 79 *q40_mem_cptr = *p++; 80 q40_mem_cptr += 4; 81 _cpleft--; 82 } 83 } 84 } 85 86 static int __init q40_debug_setup(char *arg) 87 { 88 /* useful for early debugging stages - writes kernel messages into SRAM */ 89 if (MACH_IS_Q40 && !strncmp(arg, "mem", 3)) { 90 /*printk("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/ 91 _cpleft = 2000 - ((long)q40_mem_cptr-0xff020000) / 4; 92 register_console(&q40_console_driver); 93 } 94 return 0; 95 } 96 97 early_param("debug", q40_debug_setup); 98 99 #if 0 100 void printq40(char *str) 101 { 102 int l = strlen(str); 103 char *p = q40_mem_cptr; 104 105 while (l-- > 0 && _cpleft-- > 0) { 106 *p = *str++; 107 p += 4; 108 } 109 q40_mem_cptr = p; 110 } 111 #endif 112 113 static int halted; 114 115 #ifdef CONFIG_HEARTBEAT 116 static void q40_heartbeat(int on) 117 { 118 if (halted) 119 return; 120 121 if (on) 122 Q40_LED_ON(); 123 else 124 Q40_LED_OFF(); 125 } 126 #endif 127 128 static void q40_reset(void) 129 { 130 halted = 1; 131 printk("\n\n*******************************************\n" 132 "Called q40_reset : press the RESET button!! \n" 133 "*******************************************\n"); 134 Q40_LED_ON(); 135 while (1) 136 ; 137 } 138 139 static void q40_halt(void) 140 { 141 halted = 1; 142 printk("\n\n*******************\n" 143 " Called q40_halt\n" 144 "*******************\n"); 145 Q40_LED_ON(); 146 while (1) 147 ; 148 } 149 150 static void q40_get_model(char *model) 151 { 152 sprintf(model, "Q40"); 153 } 154 155 static unsigned int serports[] = 156 { 157 0x3f8,0x2f8,0x3e8,0x2e8,0 158 }; 159 160 static void q40_disable_irqs(void) 161 { 162 unsigned i, j; 163 164 j = 0; 165 while ((i = serports[j++])) 166 outb(0, i + UART_IER); 167 master_outb(0, EXT_ENABLE_REG); 168 master_outb(0, KEY_IRQ_ENABLE_REG); 169 } 170 171 void __init config_q40(void) 172 { 173 mach_sched_init = q40_sched_init; 174 175 mach_init_IRQ = q40_init_IRQ; 176 mach_gettimeoffset = q40_gettimeoffset; 177 mach_hwclk = q40_hwclk; 178 mach_get_ss = q40_get_ss; 179 mach_get_rtc_pll = q40_get_rtc_pll; 180 mach_set_rtc_pll = q40_set_rtc_pll; 181 mach_set_clock_mmss = q40_set_clock_mmss; 182 183 mach_reset = q40_reset; 184 mach_get_model = q40_get_model; 185 186 #if defined(CONFIG_INPUT_M68K_BEEP) || defined(CONFIG_INPUT_M68K_BEEP_MODULE) 187 mach_beep = q40_mksound; 188 #endif 189 #ifdef CONFIG_HEARTBEAT 190 mach_heartbeat = q40_heartbeat; 191 #endif 192 mach_halt = q40_halt; 193 194 /* disable a few things that SMSQ might have left enabled */ 195 q40_disable_irqs(); 196 197 /* no DMA at all, but ide-scsi requires it.. make sure 198 * all physical RAM fits into the boundary - otherwise 199 * allocator may play costly and useless tricks */ 200 mach_max_dma_address = 1024*1024*1024; 201 } 202 203 204 int q40_parse_bootinfo(const struct bi_record *rec) 205 { 206 return 1; 207 } 208 209 210 static unsigned long q40_gettimeoffset(void) 211 { 212 return 5000 * (ql_ticks != 0); 213 } 214 215 216 /* 217 * Looks like op is non-zero for setting the clock, and zero for 218 * reading the clock. 219 * 220 * struct hwclk_time { 221 * unsigned sec; 0..59 222 * unsigned min; 0..59 223 * unsigned hour; 0..23 224 * unsigned day; 1..31 225 * unsigned mon; 0..11 226 * unsigned year; 00... 227 * int wday; 0..6, 0 is Sunday, -1 means unknown/don't set 228 * }; 229 */ 230 231 static int q40_hwclk(int op, struct rtc_time *t) 232 { 233 if (op) { 234 /* Write.... */ 235 Q40_RTC_CTRL |= Q40_RTC_WRITE; 236 237 Q40_RTC_SECS = bin2bcd(t->tm_sec); 238 Q40_RTC_MINS = bin2bcd(t->tm_min); 239 Q40_RTC_HOUR = bin2bcd(t->tm_hour); 240 Q40_RTC_DATE = bin2bcd(t->tm_mday); 241 Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1); 242 Q40_RTC_YEAR = bin2bcd(t->tm_year%100); 243 if (t->tm_wday >= 0) 244 Q40_RTC_DOW = bin2bcd(t->tm_wday+1); 245 246 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE); 247 } else { 248 /* Read.... */ 249 Q40_RTC_CTRL |= Q40_RTC_READ; 250 251 t->tm_year = bcd2bin (Q40_RTC_YEAR); 252 t->tm_mon = bcd2bin (Q40_RTC_MNTH)-1; 253 t->tm_mday = bcd2bin (Q40_RTC_DATE); 254 t->tm_hour = bcd2bin (Q40_RTC_HOUR); 255 t->tm_min = bcd2bin (Q40_RTC_MINS); 256 t->tm_sec = bcd2bin (Q40_RTC_SECS); 257 258 Q40_RTC_CTRL &= ~(Q40_RTC_READ); 259 260 if (t->tm_year < 70) 261 t->tm_year += 100; 262 t->tm_wday = bcd2bin(Q40_RTC_DOW)-1; 263 } 264 265 return 0; 266 } 267 268 static unsigned int q40_get_ss(void) 269 { 270 return bcd2bin(Q40_RTC_SECS); 271 } 272 273 /* 274 * Set the minutes and seconds from seconds value 'nowtime'. Fail if 275 * clock is out by > 30 minutes. Logic lifted from atari code. 276 */ 277 278 static int q40_set_clock_mmss(unsigned long nowtime) 279 { 280 int retval = 0; 281 short real_seconds = nowtime % 60, real_minutes = (nowtime / 60) % 60; 282 283 int rtc_minutes; 284 285 rtc_minutes = bcd2bin(Q40_RTC_MINS); 286 287 if ((rtc_minutes < real_minutes ? 288 real_minutes - rtc_minutes : 289 rtc_minutes - real_minutes) < 30) { 290 Q40_RTC_CTRL |= Q40_RTC_WRITE; 291 Q40_RTC_MINS = bin2bcd(real_minutes); 292 Q40_RTC_SECS = bin2bcd(real_seconds); 293 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE); 294 } else 295 retval = -1; 296 297 return retval; 298 } 299 300 301 /* get and set PLL calibration of RTC clock */ 302 #define Q40_RTC_PLL_MASK ((1<<5)-1) 303 #define Q40_RTC_PLL_SIGN (1<<5) 304 305 static int q40_get_rtc_pll(struct rtc_pll_info *pll) 306 { 307 int tmp = Q40_RTC_CTRL; 308 309 pll->pll_value = tmp & Q40_RTC_PLL_MASK; 310 if (tmp & Q40_RTC_PLL_SIGN) 311 pll->pll_value = -pll->pll_value; 312 pll->pll_max = 31; 313 pll->pll_min = -31; 314 pll->pll_posmult = 512; 315 pll->pll_negmult = 256; 316 pll->pll_clock = 125829120; 317 318 return 0; 319 } 320 321 static int q40_set_rtc_pll(struct rtc_pll_info *pll) 322 { 323 if (!pll->pll_ctrl) { 324 /* the docs are a bit unclear so I am doublesetting */ 325 /* RTC_WRITE here ... */ 326 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) | 327 Q40_RTC_WRITE; 328 Q40_RTC_CTRL |= Q40_RTC_WRITE; 329 Q40_RTC_CTRL = tmp; 330 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE); 331 return 0; 332 } else 333 return -EINVAL; 334 } 335