1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * linux/arch/m68k/mm/memory.c 4 * 5 * Copyright (C) 1995 Hamish Macdonald 6 */ 7 8 #include <linux/module.h> 9 #include <linux/mm.h> 10 #include <linux/kernel.h> 11 #include <linux/string.h> 12 #include <linux/types.h> 13 #include <linux/init.h> 14 #include <linux/pagemap.h> 15 #include <linux/gfp.h> 16 17 #include <asm/setup.h> 18 #include <asm/segment.h> 19 #include <asm/page.h> 20 #include <asm/traps.h> 21 #include <asm/machdep.h> 22 23 24 /* invalidate page in both caches */ 25 static inline void clear040(unsigned long paddr) 26 { 27 asm volatile ( 28 "nop\n\t" 29 ".chip 68040\n\t" 30 "cinvp %%bc,(%0)\n\t" 31 ".chip 68k" 32 : : "a" (paddr)); 33 } 34 35 /* invalidate page in i-cache */ 36 static inline void cleari040(unsigned long paddr) 37 { 38 asm volatile ( 39 "nop\n\t" 40 ".chip 68040\n\t" 41 "cinvp %%ic,(%0)\n\t" 42 ".chip 68k" 43 : : "a" (paddr)); 44 } 45 46 /* push page in both caches */ 47 /* RZ: cpush %bc DOES invalidate %ic, regardless of DPI */ 48 static inline void push040(unsigned long paddr) 49 { 50 asm volatile ( 51 "nop\n\t" 52 ".chip 68040\n\t" 53 "cpushp %%bc,(%0)\n\t" 54 ".chip 68k" 55 : : "a" (paddr)); 56 } 57 58 /* push and invalidate page in both caches, must disable ints 59 * to avoid invalidating valid data */ 60 static inline void pushcl040(unsigned long paddr) 61 { 62 unsigned long flags; 63 64 local_irq_save(flags); 65 push040(paddr); 66 if (CPU_IS_060) 67 clear040(paddr); 68 local_irq_restore(flags); 69 } 70 71 /* 72 * 040: Hit every page containing an address in the range paddr..paddr+len-1. 73 * (Low order bits of the ea of a CINVP/CPUSHP are "don't care"s). 74 * Hit every page until there is a page or less to go. Hit the next page, 75 * and the one after that if the range hits it. 76 */ 77 /* ++roman: A little bit more care is required here: The CINVP instruction 78 * invalidates cache entries WITHOUT WRITING DIRTY DATA BACK! So the beginning 79 * and the end of the region must be treated differently if they are not 80 * exactly at the beginning or end of a page boundary. Else, maybe too much 81 * data becomes invalidated and thus lost forever. CPUSHP does what we need: 82 * it invalidates the page after pushing dirty data to memory. (Thanks to Jes 83 * for discovering the problem!) 84 */ 85 /* ... but on the '060, CPUSH doesn't invalidate (for us, since we have set 86 * the DPI bit in the CACR; would it cause problems with temporarily changing 87 * this?). So we have to push first and then additionally to invalidate. 88 */ 89 90 91 /* 92 * cache_clear() semantics: Clear any cache entries for the area in question, 93 * without writing back dirty entries first. This is useful if the data will 94 * be overwritten anyway, e.g. by DMA to memory. The range is defined by a 95 * _physical_ address. 96 */ 97 98 void cache_clear (unsigned long paddr, int len) 99 { 100 if (CPU_IS_COLDFIRE) { 101 clear_cf_bcache(0, DCACHE_MAX_ADDR); 102 } else if (CPU_IS_040_OR_060) { 103 int tmp; 104 105 /* 106 * We need special treatment for the first page, in case it 107 * is not page-aligned. Page align the addresses to work 108 * around bug I17 in the 68060. 109 */ 110 if ((tmp = -paddr & (PAGE_SIZE - 1))) { 111 pushcl040(paddr & PAGE_MASK); 112 if ((len -= tmp) <= 0) 113 return; 114 paddr += tmp; 115 } 116 tmp = PAGE_SIZE; 117 paddr &= PAGE_MASK; 118 while ((len -= tmp) >= 0) { 119 clear040(paddr); 120 paddr += tmp; 121 } 122 if ((len += tmp)) 123 /* a page boundary gets crossed at the end */ 124 pushcl040(paddr); 125 } 126 else /* 68030 or 68020 */ 127 asm volatile ("movec %/cacr,%/d0\n\t" 128 "oriw %0,%/d0\n\t" 129 "movec %/d0,%/cacr" 130 : : "i" (FLUSH_I_AND_D) 131 : "d0"); 132 #ifdef CONFIG_M68K_L2_CACHE 133 if(mach_l2_flush) 134 mach_l2_flush(0); 135 #endif 136 } 137 EXPORT_SYMBOL(cache_clear); 138 139 140 /* 141 * cache_push() semantics: Write back any dirty cache data in the given area, 142 * and invalidate the range in the instruction cache. It needs not (but may) 143 * invalidate those entries also in the data cache. The range is defined by a 144 * _physical_ address. 145 */ 146 147 void cache_push (unsigned long paddr, int len) 148 { 149 if (CPU_IS_COLDFIRE) { 150 flush_cf_bcache(0, DCACHE_MAX_ADDR); 151 } else if (CPU_IS_040_OR_060) { 152 int tmp = PAGE_SIZE; 153 154 /* 155 * on 68040 or 68060, push cache lines for pages in the range; 156 * on the '040 this also invalidates the pushed lines, but not on 157 * the '060! 158 */ 159 len += paddr & (PAGE_SIZE - 1); 160 161 /* 162 * Work around bug I17 in the 68060 affecting some instruction 163 * lines not being invalidated properly. 164 */ 165 paddr &= PAGE_MASK; 166 167 do { 168 push040(paddr); 169 paddr += tmp; 170 } while ((len -= tmp) > 0); 171 } 172 /* 173 * 68030/68020 have no writeback cache. On the other hand, 174 * cache_push is actually a superset of cache_clear (the lines 175 * get written back and invalidated), so we should make sure 176 * to perform the corresponding actions. After all, this is getting 177 * called in places where we've just loaded code, or whatever, so 178 * flushing the icache is appropriate; flushing the dcache shouldn't 179 * be required. 180 */ 181 else /* 68030 or 68020 */ 182 asm volatile ("movec %/cacr,%/d0\n\t" 183 "oriw %0,%/d0\n\t" 184 "movec %/d0,%/cacr" 185 : : "i" (FLUSH_I) 186 : "d0"); 187 #ifdef CONFIG_M68K_L2_CACHE 188 if(mach_l2_flush) 189 mach_l2_flush(1); 190 #endif 191 } 192 EXPORT_SYMBOL(cache_push); 193 194