1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * linux/arch/m68k/mm/memory.c 4 * 5 * Copyright (C) 1995 Hamish Macdonald 6 */ 7 8 #include <linux/module.h> 9 #include <linux/mm.h> 10 #include <linux/kernel.h> 11 #include <linux/string.h> 12 #include <linux/types.h> 13 #include <linux/init.h> 14 #include <linux/pagemap.h> 15 #include <linux/gfp.h> 16 17 #include <asm/setup.h> 18 #include <asm/segment.h> 19 #include <asm/page.h> 20 #include <asm/pgalloc.h> 21 #include <asm/traps.h> 22 #include <asm/machdep.h> 23 24 25 /* invalidate page in both caches */ 26 static inline void clear040(unsigned long paddr) 27 { 28 asm volatile ( 29 "nop\n\t" 30 ".chip 68040\n\t" 31 "cinvp %%bc,(%0)\n\t" 32 ".chip 68k" 33 : : "a" (paddr)); 34 } 35 36 /* invalidate page in i-cache */ 37 static inline void cleari040(unsigned long paddr) 38 { 39 asm volatile ( 40 "nop\n\t" 41 ".chip 68040\n\t" 42 "cinvp %%ic,(%0)\n\t" 43 ".chip 68k" 44 : : "a" (paddr)); 45 } 46 47 /* push page in both caches */ 48 /* RZ: cpush %bc DOES invalidate %ic, regardless of DPI */ 49 static inline void push040(unsigned long paddr) 50 { 51 asm volatile ( 52 "nop\n\t" 53 ".chip 68040\n\t" 54 "cpushp %%bc,(%0)\n\t" 55 ".chip 68k" 56 : : "a" (paddr)); 57 } 58 59 /* push and invalidate page in both caches, must disable ints 60 * to avoid invalidating valid data */ 61 static inline void pushcl040(unsigned long paddr) 62 { 63 unsigned long flags; 64 65 local_irq_save(flags); 66 push040(paddr); 67 if (CPU_IS_060) 68 clear040(paddr); 69 local_irq_restore(flags); 70 } 71 72 /* 73 * 040: Hit every page containing an address in the range paddr..paddr+len-1. 74 * (Low order bits of the ea of a CINVP/CPUSHP are "don't care"s). 75 * Hit every page until there is a page or less to go. Hit the next page, 76 * and the one after that if the range hits it. 77 */ 78 /* ++roman: A little bit more care is required here: The CINVP instruction 79 * invalidates cache entries WITHOUT WRITING DIRTY DATA BACK! So the beginning 80 * and the end of the region must be treated differently if they are not 81 * exactly at the beginning or end of a page boundary. Else, maybe too much 82 * data becomes invalidated and thus lost forever. CPUSHP does what we need: 83 * it invalidates the page after pushing dirty data to memory. (Thanks to Jes 84 * for discovering the problem!) 85 */ 86 /* ... but on the '060, CPUSH doesn't invalidate (for us, since we have set 87 * the DPI bit in the CACR; would it cause problems with temporarily changing 88 * this?). So we have to push first and then additionally to invalidate. 89 */ 90 91 92 /* 93 * cache_clear() semantics: Clear any cache entries for the area in question, 94 * without writing back dirty entries first. This is useful if the data will 95 * be overwritten anyway, e.g. by DMA to memory. The range is defined by a 96 * _physical_ address. 97 */ 98 99 void cache_clear (unsigned long paddr, int len) 100 { 101 if (CPU_IS_COLDFIRE) { 102 clear_cf_bcache(0, DCACHE_MAX_ADDR); 103 } else if (CPU_IS_040_OR_060) { 104 int tmp; 105 106 /* 107 * We need special treatment for the first page, in case it 108 * is not page-aligned. Page align the addresses to work 109 * around bug I17 in the 68060. 110 */ 111 if ((tmp = -paddr & (PAGE_SIZE - 1))) { 112 pushcl040(paddr & PAGE_MASK); 113 if ((len -= tmp) <= 0) 114 return; 115 paddr += tmp; 116 } 117 tmp = PAGE_SIZE; 118 paddr &= PAGE_MASK; 119 while ((len -= tmp) >= 0) { 120 clear040(paddr); 121 paddr += tmp; 122 } 123 if ((len += tmp)) 124 /* a page boundary gets crossed at the end */ 125 pushcl040(paddr); 126 } 127 else /* 68030 or 68020 */ 128 asm volatile ("movec %/cacr,%/d0\n\t" 129 "oriw %0,%/d0\n\t" 130 "movec %/d0,%/cacr" 131 : : "i" (FLUSH_I_AND_D) 132 : "d0"); 133 #ifdef CONFIG_M68K_L2_CACHE 134 if(mach_l2_flush) 135 mach_l2_flush(0); 136 #endif 137 } 138 EXPORT_SYMBOL(cache_clear); 139 140 141 /* 142 * cache_push() semantics: Write back any dirty cache data in the given area, 143 * and invalidate the range in the instruction cache. It needs not (but may) 144 * invalidate those entries also in the data cache. The range is defined by a 145 * _physical_ address. 146 */ 147 148 void cache_push (unsigned long paddr, int len) 149 { 150 if (CPU_IS_COLDFIRE) { 151 flush_cf_bcache(0, DCACHE_MAX_ADDR); 152 } else if (CPU_IS_040_OR_060) { 153 int tmp = PAGE_SIZE; 154 155 /* 156 * on 68040 or 68060, push cache lines for pages in the range; 157 * on the '040 this also invalidates the pushed lines, but not on 158 * the '060! 159 */ 160 len += paddr & (PAGE_SIZE - 1); 161 162 /* 163 * Work around bug I17 in the 68060 affecting some instruction 164 * lines not being invalidated properly. 165 */ 166 paddr &= PAGE_MASK; 167 168 do { 169 push040(paddr); 170 paddr += tmp; 171 } while ((len -= tmp) > 0); 172 } 173 /* 174 * 68030/68020 have no writeback cache. On the other hand, 175 * cache_push is actually a superset of cache_clear (the lines 176 * get written back and invalidated), so we should make sure 177 * to perform the corresponding actions. After all, this is getting 178 * called in places where we've just loaded code, or whatever, so 179 * flushing the icache is appropriate; flushing the dcache shouldn't 180 * be required. 181 */ 182 else /* 68030 or 68020 */ 183 asm volatile ("movec %/cacr,%/d0\n\t" 184 "oriw %0,%/d0\n\t" 185 "movec %/d0,%/cacr" 186 : : "i" (FLUSH_I) 187 : "d0"); 188 #ifdef CONFIG_M68K_L2_CACHE 189 if(mach_l2_flush) 190 mach_l2_flush(1); 191 #endif 192 } 193 EXPORT_SYMBOL(cache_push); 194 195