1 /* 2 * linux/arch/m68k/mm/memory.c 3 * 4 * Copyright (C) 1995 Hamish Macdonald 5 */ 6 7 #include <linux/module.h> 8 #include <linux/mm.h> 9 #include <linux/kernel.h> 10 #include <linux/string.h> 11 #include <linux/types.h> 12 #include <linux/init.h> 13 #include <linux/pagemap.h> 14 #include <linux/gfp.h> 15 16 #include <asm/setup.h> 17 #include <asm/segment.h> 18 #include <asm/page.h> 19 #include <asm/pgalloc.h> 20 #include <asm/traps.h> 21 #include <asm/machdep.h> 22 23 24 /* ++andreas: {get,free}_pointer_table rewritten to use unused fields from 25 struct page instead of separately kmalloced struct. Stolen from 26 arch/sparc/mm/srmmu.c ... */ 27 28 typedef struct list_head ptable_desc; 29 static LIST_HEAD(ptable_list); 30 31 #define PD_PTABLE(page) ((ptable_desc *)&(virt_to_page(page)->lru)) 32 #define PD_PAGE(ptable) (list_entry(ptable, struct page, lru)) 33 #define PD_MARKBITS(dp) (*(unsigned char *)&PD_PAGE(dp)->index) 34 35 #define PTABLE_SIZE (PTRS_PER_PMD * sizeof(pmd_t)) 36 37 void __init init_pointer_table(unsigned long ptable) 38 { 39 ptable_desc *dp; 40 unsigned long page = ptable & PAGE_MASK; 41 unsigned char mask = 1 << ((ptable - page)/PTABLE_SIZE); 42 43 dp = PD_PTABLE(page); 44 if (!(PD_MARKBITS(dp) & mask)) { 45 PD_MARKBITS(dp) = 0xff; 46 list_add(dp, &ptable_list); 47 } 48 49 PD_MARKBITS(dp) &= ~mask; 50 pr_debug("init_pointer_table: %lx, %x\n", ptable, PD_MARKBITS(dp)); 51 52 /* unreserve the page so it's possible to free that page */ 53 PD_PAGE(dp)->flags &= ~(1 << PG_reserved); 54 init_page_count(PD_PAGE(dp)); 55 56 return; 57 } 58 59 pmd_t *get_pointer_table (void) 60 { 61 ptable_desc *dp = ptable_list.next; 62 unsigned char mask = PD_MARKBITS (dp); 63 unsigned char tmp; 64 unsigned int off; 65 66 /* 67 * For a pointer table for a user process address space, a 68 * table is taken from a page allocated for the purpose. Each 69 * page can hold 8 pointer tables. The page is remapped in 70 * virtual address space to be noncacheable. 71 */ 72 if (mask == 0) { 73 void *page; 74 ptable_desc *new; 75 76 if (!(page = (void *)get_zeroed_page(GFP_KERNEL))) 77 return NULL; 78 79 flush_tlb_kernel_page(page); 80 nocache_page(page); 81 82 new = PD_PTABLE(page); 83 PD_MARKBITS(new) = 0xfe; 84 list_add_tail(new, dp); 85 86 return (pmd_t *)page; 87 } 88 89 for (tmp = 1, off = 0; (mask & tmp) == 0; tmp <<= 1, off += PTABLE_SIZE) 90 ; 91 PD_MARKBITS(dp) = mask & ~tmp; 92 if (!PD_MARKBITS(dp)) { 93 /* move to end of list */ 94 list_move_tail(dp, &ptable_list); 95 } 96 return (pmd_t *) (page_address(PD_PAGE(dp)) + off); 97 } 98 99 int free_pointer_table (pmd_t *ptable) 100 { 101 ptable_desc *dp; 102 unsigned long page = (unsigned long)ptable & PAGE_MASK; 103 unsigned char mask = 1 << (((unsigned long)ptable - page)/PTABLE_SIZE); 104 105 dp = PD_PTABLE(page); 106 if (PD_MARKBITS (dp) & mask) 107 panic ("table already free!"); 108 109 PD_MARKBITS (dp) |= mask; 110 111 if (PD_MARKBITS(dp) == 0xff) { 112 /* all tables in page are free, free page */ 113 list_del(dp); 114 cache_page((void *)page); 115 free_page (page); 116 return 1; 117 } else if (ptable_list.next != dp) { 118 /* 119 * move this descriptor to the front of the list, since 120 * it has one or more free tables. 121 */ 122 list_move(dp, &ptable_list); 123 } 124 return 0; 125 } 126 127 /* invalidate page in both caches */ 128 static inline void clear040(unsigned long paddr) 129 { 130 asm volatile ( 131 "nop\n\t" 132 ".chip 68040\n\t" 133 "cinvp %%bc,(%0)\n\t" 134 ".chip 68k" 135 : : "a" (paddr)); 136 } 137 138 /* invalidate page in i-cache */ 139 static inline void cleari040(unsigned long paddr) 140 { 141 asm volatile ( 142 "nop\n\t" 143 ".chip 68040\n\t" 144 "cinvp %%ic,(%0)\n\t" 145 ".chip 68k" 146 : : "a" (paddr)); 147 } 148 149 /* push page in both caches */ 150 /* RZ: cpush %bc DOES invalidate %ic, regardless of DPI */ 151 static inline void push040(unsigned long paddr) 152 { 153 asm volatile ( 154 "nop\n\t" 155 ".chip 68040\n\t" 156 "cpushp %%bc,(%0)\n\t" 157 ".chip 68k" 158 : : "a" (paddr)); 159 } 160 161 /* push and invalidate page in both caches, must disable ints 162 * to avoid invalidating valid data */ 163 static inline void pushcl040(unsigned long paddr) 164 { 165 unsigned long flags; 166 167 local_irq_save(flags); 168 push040(paddr); 169 if (CPU_IS_060) 170 clear040(paddr); 171 local_irq_restore(flags); 172 } 173 174 /* 175 * 040: Hit every page containing an address in the range paddr..paddr+len-1. 176 * (Low order bits of the ea of a CINVP/CPUSHP are "don't care"s). 177 * Hit every page until there is a page or less to go. Hit the next page, 178 * and the one after that if the range hits it. 179 */ 180 /* ++roman: A little bit more care is required here: The CINVP instruction 181 * invalidates cache entries WITHOUT WRITING DIRTY DATA BACK! So the beginning 182 * and the end of the region must be treated differently if they are not 183 * exactly at the beginning or end of a page boundary. Else, maybe too much 184 * data becomes invalidated and thus lost forever. CPUSHP does what we need: 185 * it invalidates the page after pushing dirty data to memory. (Thanks to Jes 186 * for discovering the problem!) 187 */ 188 /* ... but on the '060, CPUSH doesn't invalidate (for us, since we have set 189 * the DPI bit in the CACR; would it cause problems with temporarily changing 190 * this?). So we have to push first and then additionally to invalidate. 191 */ 192 193 194 /* 195 * cache_clear() semantics: Clear any cache entries for the area in question, 196 * without writing back dirty entries first. This is useful if the data will 197 * be overwritten anyway, e.g. by DMA to memory. The range is defined by a 198 * _physical_ address. 199 */ 200 201 void cache_clear (unsigned long paddr, int len) 202 { 203 if (CPU_IS_COLDFIRE) { 204 clear_cf_bcache(0, DCACHE_MAX_ADDR); 205 } else if (CPU_IS_040_OR_060) { 206 int tmp; 207 208 /* 209 * We need special treatment for the first page, in case it 210 * is not page-aligned. Page align the addresses to work 211 * around bug I17 in the 68060. 212 */ 213 if ((tmp = -paddr & (PAGE_SIZE - 1))) { 214 pushcl040(paddr & PAGE_MASK); 215 if ((len -= tmp) <= 0) 216 return; 217 paddr += tmp; 218 } 219 tmp = PAGE_SIZE; 220 paddr &= PAGE_MASK; 221 while ((len -= tmp) >= 0) { 222 clear040(paddr); 223 paddr += tmp; 224 } 225 if ((len += tmp)) 226 /* a page boundary gets crossed at the end */ 227 pushcl040(paddr); 228 } 229 else /* 68030 or 68020 */ 230 asm volatile ("movec %/cacr,%/d0\n\t" 231 "oriw %0,%/d0\n\t" 232 "movec %/d0,%/cacr" 233 : : "i" (FLUSH_I_AND_D) 234 : "d0"); 235 #ifdef CONFIG_M68K_L2_CACHE 236 if(mach_l2_flush) 237 mach_l2_flush(0); 238 #endif 239 } 240 EXPORT_SYMBOL(cache_clear); 241 242 243 /* 244 * cache_push() semantics: Write back any dirty cache data in the given area, 245 * and invalidate the range in the instruction cache. It needs not (but may) 246 * invalidate those entries also in the data cache. The range is defined by a 247 * _physical_ address. 248 */ 249 250 void cache_push (unsigned long paddr, int len) 251 { 252 if (CPU_IS_COLDFIRE) { 253 flush_cf_bcache(0, DCACHE_MAX_ADDR); 254 } else if (CPU_IS_040_OR_060) { 255 int tmp = PAGE_SIZE; 256 257 /* 258 * on 68040 or 68060, push cache lines for pages in the range; 259 * on the '040 this also invalidates the pushed lines, but not on 260 * the '060! 261 */ 262 len += paddr & (PAGE_SIZE - 1); 263 264 /* 265 * Work around bug I17 in the 68060 affecting some instruction 266 * lines not being invalidated properly. 267 */ 268 paddr &= PAGE_MASK; 269 270 do { 271 push040(paddr); 272 paddr += tmp; 273 } while ((len -= tmp) > 0); 274 } 275 /* 276 * 68030/68020 have no writeback cache. On the other hand, 277 * cache_push is actually a superset of cache_clear (the lines 278 * get written back and invalidated), so we should make sure 279 * to perform the corresponding actions. After all, this is getting 280 * called in places where we've just loaded code, or whatever, so 281 * flushing the icache is appropriate; flushing the dcache shouldn't 282 * be required. 283 */ 284 else /* 68030 or 68020 */ 285 asm volatile ("movec %/cacr,%/d0\n\t" 286 "oriw %0,%/d0\n\t" 287 "movec %/d0,%/cacr" 288 : : "i" (FLUSH_I) 289 : "d0"); 290 #ifdef CONFIG_M68K_L2_CACHE 291 if(mach_l2_flush) 292 mach_l2_flush(1); 293 #endif 294 } 295 EXPORT_SYMBOL(cache_push); 296 297