1 /* 2 * I/O Processor (IOP) management 3 * Written and (C) 1999 by Joshua M. Thompson (funaho@jurai.org) 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice and this list of conditions. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice and this list of conditions in the documentation and/or other 12 * materials provided with the distribution. 13 */ 14 15 /* 16 * The IOP chips are used in the IIfx and some Quadras (900, 950) to manage 17 * serial and ADB. They are actually a 6502 processor and some glue logic. 18 * 19 * 990429 (jmt) - Initial implementation, just enough to knock the SCC IOP 20 * into compatible mode so nobody has to fiddle with the 21 * Serial Switch control panel anymore. 22 * 990603 (jmt) - Added code to grab the correct ISM IOP interrupt for OSS 23 * and non-OSS machines (at least I hope it's correct on a 24 * non-OSS machine -- someone with a Q900 or Q950 needs to 25 * check this.) 26 * 990605 (jmt) - Rearranged things a bit wrt IOP detection; iop_present is 27 * gone, IOP base addresses are now in an array and the 28 * globally-visible functions take an IOP number instead of an 29 * an actual base address. 30 * 990610 (jmt) - Finished the message passing framework and it seems to work. 31 * Sending _definitely_ works; my adb-bus.c mods can send 32 * messages and receive the MSG_COMPLETED status back from the 33 * IOP. The trick now is figuring out the message formats. 34 * 990611 (jmt) - More cleanups. Fixed problem where unclaimed messages on a 35 * receive channel were never properly acknowledged. Bracketed 36 * the remaining debug printk's with #ifdef's and disabled 37 * debugging. I can now type on the console. 38 * 990612 (jmt) - Copyright notice added. Reworked the way replies are handled. 39 * It turns out that replies are placed back in the send buffer 40 * for that channel; messages on the receive channels are always 41 * unsolicited messages from the IOP (and our replies to them 42 * should go back in the receive channel.) Also added tracking 43 * of device names to the listener functions ala the interrupt 44 * handlers. 45 * 990729 (jmt) - Added passing of pt_regs structure to IOP handlers. This is 46 * used by the new unified ADB driver. 47 * 48 * TODO: 49 * 50 * o Something should be periodically checking iop_alive() to make sure the 51 * IOP hasn't died. 52 * o Some of the IOP manager routines need better error checking and 53 * return codes. Nothing major, just prettying up. 54 */ 55 56 /* 57 * ----------------------- 58 * IOP Message Passing 101 59 * ----------------------- 60 * 61 * The host talks to the IOPs using a rather simple message-passing scheme via 62 * a shared memory area in the IOP RAM. Each IOP has seven "channels"; each 63 * channel is conneced to a specific software driver on the IOP. For example 64 * on the SCC IOP there is one channel for each serial port. Each channel has 65 * an incoming and and outgoing message queue with a depth of one. 66 * 67 * A message is 32 bytes plus a state byte for the channel (MSG_IDLE, MSG_NEW, 68 * MSG_RCVD, MSG_COMPLETE). To send a message you copy the message into the 69 * buffer, set the state to MSG_NEW and signal the IOP by setting the IRQ flag 70 * in the IOP control to 1. The IOP will move the state to MSG_RCVD when it 71 * receives the message and then to MSG_COMPLETE when the message processing 72 * has completed. It is the host's responsibility at that point to read the 73 * reply back out of the send channel buffer and reset the channel state back 74 * to MSG_IDLE. 75 * 76 * To receive message from the IOP the same procedure is used except the roles 77 * are reversed. That is, the IOP puts message in the channel with a state of 78 * MSG_NEW, and the host receives the message and move its state to MSG_RCVD 79 * and then to MSG_COMPLETE when processing is completed and the reply (if any) 80 * has been placed back in the receive channel. The IOP will then reset the 81 * channel state to MSG_IDLE. 82 * 83 * Two sets of host interrupts are provided, INT0 and INT1. Both appear on one 84 * interrupt level; they are distinguished by a pair of bits in the IOP status 85 * register. The IOP will raise INT0 when one or more messages in the send 86 * channels have gone to the MSG_COMPLETE state and it will raise INT1 when one 87 * or more messages on the receive channels have gone to the MSG_NEW state. 88 * 89 * Since each channel handles only one message we have to implement a small 90 * interrupt-driven queue on our end. Messages to be sent are placed on the 91 * queue for sending and contain a pointer to an optional callback function. 92 * The handler for a message is called when the message state goes to 93 * MSG_COMPLETE. 94 * 95 * For receiving message we maintain a list of handler functions to call when 96 * a message is received on that IOP/channel combination. The handlers are 97 * called much like an interrupt handler and are passed a copy of the message 98 * from the IOP. The message state will be in MSG_RCVD while the handler runs; 99 * it is the handler's responsibility to call iop_complete_message() when 100 * finished; this function moves the message state to MSG_COMPLETE and signals 101 * the IOP. This two-step process is provided to allow the handler to defer 102 * message processing to a bottom-half handler if the processing will take 103 * a signifigant amount of time (handlers are called at interrupt time so they 104 * should execute quickly.) 105 */ 106 107 #include <linux/types.h> 108 #include <linux/kernel.h> 109 #include <linux/mm.h> 110 #include <linux/delay.h> 111 #include <linux/init.h> 112 #include <linux/proc_fs.h> 113 #include <linux/interrupt.h> 114 115 #include <asm/bootinfo.h> 116 #include <asm/macintosh.h> 117 #include <asm/macints.h> 118 #include <asm/mac_iop.h> 119 #include <asm/mac_oss.h> 120 121 /*#define DEBUG_IOP*/ 122 123 /* Set to nonezero if the IOPs are present. Set by iop_init() */ 124 125 int iop_scc_present,iop_ism_present; 126 127 #ifdef CONFIG_PROC_FS 128 static int iop_get_proc_info(char *, char **, off_t, int); 129 #endif /* CONFIG_PROC_FS */ 130 131 /* structure for tracking channel listeners */ 132 133 struct listener { 134 const char *devname; 135 void (*handler)(struct iop_msg *); 136 }; 137 138 /* 139 * IOP structures for the two IOPs 140 * 141 * The SCC IOP controls both serial ports (A and B) as its two functions. 142 * The ISM IOP controls the SWIM (floppy drive) and ADB. 143 */ 144 145 static volatile struct mac_iop *iop_base[NUM_IOPS]; 146 147 /* 148 * IOP message queues 149 */ 150 151 static struct iop_msg iop_msg_pool[NUM_IOP_MSGS]; 152 static struct iop_msg *iop_send_queue[NUM_IOPS][NUM_IOP_CHAN]; 153 static struct listener iop_listeners[NUM_IOPS][NUM_IOP_CHAN]; 154 155 irqreturn_t iop_ism_irq(int, void *); 156 157 extern void oss_irq_enable(int); 158 159 /* 160 * Private access functions 161 */ 162 163 static __inline__ void iop_loadaddr(volatile struct mac_iop *iop, __u16 addr) 164 { 165 iop->ram_addr_lo = addr; 166 iop->ram_addr_hi = addr >> 8; 167 } 168 169 static __inline__ __u8 iop_readb(volatile struct mac_iop *iop, __u16 addr) 170 { 171 iop->ram_addr_lo = addr; 172 iop->ram_addr_hi = addr >> 8; 173 return iop->ram_data; 174 } 175 176 static __inline__ void iop_writeb(volatile struct mac_iop *iop, __u16 addr, __u8 data) 177 { 178 iop->ram_addr_lo = addr; 179 iop->ram_addr_hi = addr >> 8; 180 iop->ram_data = data; 181 } 182 183 static __inline__ void iop_stop(volatile struct mac_iop *iop) 184 { 185 iop->status_ctrl &= ~IOP_RUN; 186 } 187 188 static __inline__ void iop_start(volatile struct mac_iop *iop) 189 { 190 iop->status_ctrl = IOP_RUN | IOP_AUTOINC; 191 } 192 193 static __inline__ void iop_bypass(volatile struct mac_iop *iop) 194 { 195 iop->status_ctrl |= IOP_BYPASS; 196 } 197 198 static __inline__ void iop_interrupt(volatile struct mac_iop *iop) 199 { 200 iop->status_ctrl |= IOP_IRQ; 201 } 202 203 static int iop_alive(volatile struct mac_iop *iop) 204 { 205 int retval; 206 207 retval = (iop_readb(iop, IOP_ADDR_ALIVE) == 0xFF); 208 iop_writeb(iop, IOP_ADDR_ALIVE, 0); 209 return retval; 210 } 211 212 static struct iop_msg *iop_alloc_msg(void) 213 { 214 int i; 215 unsigned long flags; 216 217 local_irq_save(flags); 218 219 for (i = 0 ; i < NUM_IOP_MSGS ; i++) { 220 if (iop_msg_pool[i].status == IOP_MSGSTATUS_UNUSED) { 221 iop_msg_pool[i].status = IOP_MSGSTATUS_WAITING; 222 local_irq_restore(flags); 223 return &iop_msg_pool[i]; 224 } 225 } 226 227 local_irq_restore(flags); 228 return NULL; 229 } 230 231 static void iop_free_msg(struct iop_msg *msg) 232 { 233 msg->status = IOP_MSGSTATUS_UNUSED; 234 } 235 236 /* 237 * This is called by the startup code before anything else. Its purpose 238 * is to find and initialize the IOPs early in the boot sequence, so that 239 * the serial IOP can be placed into bypass mode _before_ we try to 240 * initialize the serial console. 241 */ 242 243 void __init iop_preinit(void) 244 { 245 if (macintosh_config->scc_type == MAC_SCC_IOP) { 246 if (macintosh_config->ident == MAC_MODEL_IIFX) { 247 iop_base[IOP_NUM_SCC] = (struct mac_iop *) SCC_IOP_BASE_IIFX; 248 } else { 249 iop_base[IOP_NUM_SCC] = (struct mac_iop *) SCC_IOP_BASE_QUADRA; 250 } 251 iop_base[IOP_NUM_SCC]->status_ctrl = 0x87; 252 iop_scc_present = 1; 253 } else { 254 iop_base[IOP_NUM_SCC] = NULL; 255 iop_scc_present = 0; 256 } 257 if (macintosh_config->adb_type == MAC_ADB_IOP) { 258 if (macintosh_config->ident == MAC_MODEL_IIFX) { 259 iop_base[IOP_NUM_ISM] = (struct mac_iop *) ISM_IOP_BASE_IIFX; 260 } else { 261 iop_base[IOP_NUM_ISM] = (struct mac_iop *) ISM_IOP_BASE_QUADRA; 262 } 263 iop_base[IOP_NUM_ISM]->status_ctrl = 0; 264 iop_ism_present = 1; 265 } else { 266 iop_base[IOP_NUM_ISM] = NULL; 267 iop_ism_present = 0; 268 } 269 } 270 271 /* 272 * Initialize the IOPs, if present. 273 */ 274 275 void __init iop_init(void) 276 { 277 int i; 278 279 if (iop_scc_present) { 280 printk("IOP: detected SCC IOP at %p\n", iop_base[IOP_NUM_SCC]); 281 } 282 if (iop_ism_present) { 283 printk("IOP: detected ISM IOP at %p\n", iop_base[IOP_NUM_ISM]); 284 iop_start(iop_base[IOP_NUM_ISM]); 285 iop_alive(iop_base[IOP_NUM_ISM]); /* clears the alive flag */ 286 } 287 288 /* Make the whole pool available and empty the queues */ 289 290 for (i = 0 ; i < NUM_IOP_MSGS ; i++) { 291 iop_msg_pool[i].status = IOP_MSGSTATUS_UNUSED; 292 } 293 294 for (i = 0 ; i < NUM_IOP_CHAN ; i++) { 295 iop_send_queue[IOP_NUM_SCC][i] = NULL; 296 iop_send_queue[IOP_NUM_ISM][i] = NULL; 297 iop_listeners[IOP_NUM_SCC][i].devname = NULL; 298 iop_listeners[IOP_NUM_SCC][i].handler = NULL; 299 iop_listeners[IOP_NUM_ISM][i].devname = NULL; 300 iop_listeners[IOP_NUM_ISM][i].handler = NULL; 301 } 302 303 #if 0 /* Crashing in 2.4 now, not yet sure why. --jmt */ 304 #ifdef CONFIG_PROC_FS 305 create_proc_info_entry("mac_iop", 0, &proc_root, iop_get_proc_info); 306 #endif 307 #endif 308 } 309 310 /* 311 * Register the interrupt handler for the IOPs. 312 * TODO: might be wrong for non-OSS machines. Anyone? 313 */ 314 315 void __init iop_register_interrupts(void) 316 { 317 if (iop_ism_present) { 318 if (oss_present) { 319 request_irq(OSS_IRQLEV_IOPISM, iop_ism_irq, 320 IRQ_FLG_LOCK, "ISM IOP", 321 (void *) IOP_NUM_ISM); 322 oss_irq_enable(IRQ_MAC_ADB); 323 } else { 324 request_irq(IRQ_VIA2_0, iop_ism_irq, 325 IRQ_FLG_LOCK|IRQ_FLG_FAST, "ISM IOP", 326 (void *) IOP_NUM_ISM); 327 } 328 if (!iop_alive(iop_base[IOP_NUM_ISM])) { 329 printk("IOP: oh my god, they killed the ISM IOP!\n"); 330 } else { 331 printk("IOP: the ISM IOP seems to be alive.\n"); 332 } 333 } 334 } 335 336 /* 337 * Register or unregister a listener for a specific IOP and channel 338 * 339 * If the handler pointer is NULL the current listener (if any) is 340 * unregistered. Otherwise the new listener is registered provided 341 * there is no existing listener registered. 342 */ 343 344 int iop_listen(uint iop_num, uint chan, 345 void (*handler)(struct iop_msg *), 346 const char *devname) 347 { 348 if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return -EINVAL; 349 if (chan >= NUM_IOP_CHAN) return -EINVAL; 350 if (iop_listeners[iop_num][chan].handler && handler) return -EINVAL; 351 iop_listeners[iop_num][chan].devname = devname; 352 iop_listeners[iop_num][chan].handler = handler; 353 return 0; 354 } 355 356 /* 357 * Complete reception of a message, which just means copying the reply 358 * into the buffer, setting the channel state to MSG_COMPLETE and 359 * notifying the IOP. 360 */ 361 362 void iop_complete_message(struct iop_msg *msg) 363 { 364 int iop_num = msg->iop_num; 365 int chan = msg->channel; 366 int i,offset; 367 368 #ifdef DEBUG_IOP 369 printk("iop_complete(%p): iop %d chan %d\n", msg, msg->iop_num, msg->channel); 370 #endif 371 372 offset = IOP_ADDR_RECV_MSG + (msg->channel * IOP_MSG_LEN); 373 374 for (i = 0 ; i < IOP_MSG_LEN ; i++, offset++) { 375 iop_writeb(iop_base[iop_num], offset, msg->reply[i]); 376 } 377 378 iop_writeb(iop_base[iop_num], 379 IOP_ADDR_RECV_STATE + chan, IOP_MSG_COMPLETE); 380 iop_interrupt(iop_base[msg->iop_num]); 381 382 iop_free_msg(msg); 383 } 384 385 /* 386 * Actually put a message into a send channel buffer 387 */ 388 389 static void iop_do_send(struct iop_msg *msg) 390 { 391 volatile struct mac_iop *iop = iop_base[msg->iop_num]; 392 int i,offset; 393 394 offset = IOP_ADDR_SEND_MSG + (msg->channel * IOP_MSG_LEN); 395 396 for (i = 0 ; i < IOP_MSG_LEN ; i++, offset++) { 397 iop_writeb(iop, offset, msg->message[i]); 398 } 399 400 iop_writeb(iop, IOP_ADDR_SEND_STATE + msg->channel, IOP_MSG_NEW); 401 402 iop_interrupt(iop); 403 } 404 405 /* 406 * Handle sending a message on a channel that 407 * has gone into the IOP_MSG_COMPLETE state. 408 */ 409 410 static void iop_handle_send(uint iop_num, uint chan) 411 { 412 volatile struct mac_iop *iop = iop_base[iop_num]; 413 struct iop_msg *msg,*msg2; 414 int i,offset; 415 416 #ifdef DEBUG_IOP 417 printk("iop_handle_send: iop %d channel %d\n", iop_num, chan); 418 #endif 419 420 iop_writeb(iop, IOP_ADDR_SEND_STATE + chan, IOP_MSG_IDLE); 421 422 if (!(msg = iop_send_queue[iop_num][chan])) return; 423 424 msg->status = IOP_MSGSTATUS_COMPLETE; 425 offset = IOP_ADDR_SEND_MSG + (chan * IOP_MSG_LEN); 426 for (i = 0 ; i < IOP_MSG_LEN ; i++, offset++) { 427 msg->reply[i] = iop_readb(iop, offset); 428 } 429 if (msg->handler) (*msg->handler)(msg); 430 msg2 = msg; 431 msg = msg->next; 432 iop_free_msg(msg2); 433 434 iop_send_queue[iop_num][chan] = msg; 435 if (msg) iop_do_send(msg); 436 } 437 438 /* 439 * Handle reception of a message on a channel that has 440 * gone into the IOP_MSG_NEW state. 441 */ 442 443 static void iop_handle_recv(uint iop_num, uint chan) 444 { 445 volatile struct mac_iop *iop = iop_base[iop_num]; 446 int i,offset; 447 struct iop_msg *msg; 448 449 #ifdef DEBUG_IOP 450 printk("iop_handle_recv: iop %d channel %d\n", iop_num, chan); 451 #endif 452 453 msg = iop_alloc_msg(); 454 msg->iop_num = iop_num; 455 msg->channel = chan; 456 msg->status = IOP_MSGSTATUS_UNSOL; 457 msg->handler = iop_listeners[iop_num][chan].handler; 458 459 offset = IOP_ADDR_RECV_MSG + (chan * IOP_MSG_LEN); 460 461 for (i = 0 ; i < IOP_MSG_LEN ; i++, offset++) { 462 msg->message[i] = iop_readb(iop, offset); 463 } 464 465 iop_writeb(iop, IOP_ADDR_RECV_STATE + chan, IOP_MSG_RCVD); 466 467 /* If there is a listener, call it now. Otherwise complete */ 468 /* the message ourselves to avoid possible stalls. */ 469 470 if (msg->handler) { 471 (*msg->handler)(msg); 472 } else { 473 #ifdef DEBUG_IOP 474 printk("iop_handle_recv: unclaimed message on iop %d channel %d\n", iop_num, chan); 475 printk("iop_handle_recv:"); 476 for (i = 0 ; i < IOP_MSG_LEN ; i++) { 477 printk(" %02X", (uint) msg->message[i]); 478 } 479 printk("\n"); 480 #endif 481 iop_complete_message(msg); 482 } 483 } 484 485 /* 486 * Send a message 487 * 488 * The message is placed at the end of the send queue. Afterwards if the 489 * channel is idle we force an immediate send of the next message in the 490 * queue. 491 */ 492 493 int iop_send_message(uint iop_num, uint chan, void *privdata, 494 uint msg_len, __u8 *msg_data, 495 void (*handler)(struct iop_msg *)) 496 { 497 struct iop_msg *msg, *q; 498 499 if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return -EINVAL; 500 if (chan >= NUM_IOP_CHAN) return -EINVAL; 501 if (msg_len > IOP_MSG_LEN) return -EINVAL; 502 503 msg = iop_alloc_msg(); 504 if (!msg) return -ENOMEM; 505 506 msg->next = NULL; 507 msg->status = IOP_MSGSTATUS_WAITING; 508 msg->iop_num = iop_num; 509 msg->channel = chan; 510 msg->caller_priv = privdata; 511 memcpy(msg->message, msg_data, msg_len); 512 msg->handler = handler; 513 514 if (!(q = iop_send_queue[iop_num][chan])) { 515 iop_send_queue[iop_num][chan] = msg; 516 } else { 517 while (q->next) q = q->next; 518 q->next = msg; 519 } 520 521 if (iop_readb(iop_base[iop_num], 522 IOP_ADDR_SEND_STATE + chan) == IOP_MSG_IDLE) { 523 iop_do_send(msg); 524 } 525 526 return 0; 527 } 528 529 /* 530 * Upload code to the shared RAM of an IOP. 531 */ 532 533 void iop_upload_code(uint iop_num, __u8 *code_start, 534 uint code_len, __u16 shared_ram_start) 535 { 536 if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return; 537 538 iop_loadaddr(iop_base[iop_num], shared_ram_start); 539 540 while (code_len--) { 541 iop_base[iop_num]->ram_data = *code_start++; 542 } 543 } 544 545 /* 546 * Download code from the shared RAM of an IOP. 547 */ 548 549 void iop_download_code(uint iop_num, __u8 *code_start, 550 uint code_len, __u16 shared_ram_start) 551 { 552 if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return; 553 554 iop_loadaddr(iop_base[iop_num], shared_ram_start); 555 556 while (code_len--) { 557 *code_start++ = iop_base[iop_num]->ram_data; 558 } 559 } 560 561 /* 562 * Compare the code in the shared RAM of an IOP with a copy in system memory 563 * and return 0 on match or the first nonmatching system memory address on 564 * failure. 565 */ 566 567 __u8 *iop_compare_code(uint iop_num, __u8 *code_start, 568 uint code_len, __u16 shared_ram_start) 569 { 570 if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return code_start; 571 572 iop_loadaddr(iop_base[iop_num], shared_ram_start); 573 574 while (code_len--) { 575 if (*code_start != iop_base[iop_num]->ram_data) { 576 return code_start; 577 } 578 code_start++; 579 } 580 return (__u8 *) 0; 581 } 582 583 /* 584 * Handle an ISM IOP interrupt 585 */ 586 587 irqreturn_t iop_ism_irq(int irq, void *dev_id) 588 { 589 uint iop_num = (uint) dev_id; 590 volatile struct mac_iop *iop = iop_base[iop_num]; 591 int i,state; 592 593 #ifdef DEBUG_IOP 594 printk("iop_ism_irq: status = %02X\n", (uint) iop->status_ctrl); 595 #endif 596 597 /* INT0 indicates a state change on an outgoing message channel */ 598 599 if (iop->status_ctrl & IOP_INT0) { 600 iop->status_ctrl = IOP_INT0 | IOP_RUN | IOP_AUTOINC; 601 #ifdef DEBUG_IOP 602 printk("iop_ism_irq: new status = %02X, send states", 603 (uint) iop->status_ctrl); 604 #endif 605 for (i = 0 ; i < NUM_IOP_CHAN ; i++) { 606 state = iop_readb(iop, IOP_ADDR_SEND_STATE + i); 607 #ifdef DEBUG_IOP 608 printk(" %02X", state); 609 #endif 610 if (state == IOP_MSG_COMPLETE) { 611 iop_handle_send(iop_num, i); 612 } 613 } 614 #ifdef DEBUG_IOP 615 printk("\n"); 616 #endif 617 } 618 619 if (iop->status_ctrl & IOP_INT1) { /* INT1 for incoming msgs */ 620 iop->status_ctrl = IOP_INT1 | IOP_RUN | IOP_AUTOINC; 621 #ifdef DEBUG_IOP 622 printk("iop_ism_irq: new status = %02X, recv states", 623 (uint) iop->status_ctrl); 624 #endif 625 for (i = 0 ; i < NUM_IOP_CHAN ; i++) { 626 state = iop_readb(iop, IOP_ADDR_RECV_STATE + i); 627 #ifdef DEBUG_IOP 628 printk(" %02X", state); 629 #endif 630 if (state == IOP_MSG_NEW) { 631 iop_handle_recv(iop_num, i); 632 } 633 } 634 #ifdef DEBUG_IOP 635 printk("\n"); 636 #endif 637 } 638 return IRQ_HANDLED; 639 } 640 641 #ifdef CONFIG_PROC_FS 642 643 char *iop_chan_state(int state) 644 { 645 switch(state) { 646 case IOP_MSG_IDLE : return "idle "; 647 case IOP_MSG_NEW : return "new "; 648 case IOP_MSG_RCVD : return "received "; 649 case IOP_MSG_COMPLETE : return "completed "; 650 default : return "unknown "; 651 } 652 } 653 654 int iop_dump_one_iop(char *buf, int iop_num, char *iop_name) 655 { 656 int i,len = 0; 657 volatile struct mac_iop *iop = iop_base[iop_num]; 658 659 len += sprintf(buf+len, "%s IOP channel states:\n\n", iop_name); 660 len += sprintf(buf+len, "## send_state recv_state device\n"); 661 len += sprintf(buf+len, "------------------------------------------------\n"); 662 for (i = 0 ; i < NUM_IOP_CHAN ; i++) { 663 len += sprintf(buf+len, "%2d %10s %10s %s\n", i, 664 iop_chan_state(iop_readb(iop, IOP_ADDR_SEND_STATE+i)), 665 iop_chan_state(iop_readb(iop, IOP_ADDR_RECV_STATE+i)), 666 iop_listeners[iop_num][i].handler? 667 iop_listeners[iop_num][i].devname : ""); 668 669 } 670 len += sprintf(buf+len, "\n"); 671 return len; 672 } 673 674 static int iop_get_proc_info(char *buf, char **start, off_t pos, int count) 675 { 676 int len, cnt; 677 678 cnt = 0; 679 len = sprintf(buf, "IOPs detected:\n\n"); 680 681 if (iop_scc_present) { 682 len += sprintf(buf+len, "SCC IOP (%p): status %02X\n", 683 iop_base[IOP_NUM_SCC], 684 (uint) iop_base[IOP_NUM_SCC]->status_ctrl); 685 } 686 if (iop_ism_present) { 687 len += sprintf(buf+len, "ISM IOP (%p): status %02X\n\n", 688 iop_base[IOP_NUM_ISM], 689 (uint) iop_base[IOP_NUM_ISM]->status_ctrl); 690 } 691 692 if (iop_scc_present) { 693 len += iop_dump_one_iop(buf+len, IOP_NUM_SCC, "SCC"); 694 695 } 696 697 if (iop_ism_present) { 698 len += iop_dump_one_iop(buf+len, IOP_NUM_ISM, "ISM"); 699 700 } 701 702 if (len >= pos) { 703 if (!*start) { 704 *start = buf + pos; 705 cnt = len - pos; 706 } else { 707 cnt += len; 708 } 709 } 710 return (count > cnt) ? cnt : count; 711 } 712 713 #endif /* CONFIG_PROC_FS */ 714