1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 249148020SSam Ravnborg /* 349148020SSam Ravnborg * Q40 master Chip Control 486a8280aSAndrea Gelmini * RTC stuff merged for compactness. 549148020SSam Ravnborg */ 649148020SSam Ravnborg 749148020SSam Ravnborg #ifndef _Q40_MASTER_H 849148020SSam Ravnborg #define _Q40_MASTER_H 949148020SSam Ravnborg 1049148020SSam Ravnborg #include <asm/raw_io.h> 119746882fSGreg Ungerer #include <asm/kmap.h> 1249148020SSam Ravnborg 1349148020SSam Ravnborg #define q40_master_addr 0xff000000 1449148020SSam Ravnborg 1549148020SSam Ravnborg #define IIRQ_REG 0x0 /* internal IRQ reg */ 1649148020SSam Ravnborg #define EIRQ_REG 0x4 /* external ... */ 1749148020SSam Ravnborg #define KEYCODE_REG 0x1c /* value of received scancode */ 1849148020SSam Ravnborg #define DISPLAY_CONTROL_REG 0x18 1949148020SSam Ravnborg #define FRAME_CLEAR_REG 0x24 2049148020SSam Ravnborg #define LED_REG 0x30 2149148020SSam Ravnborg 2249148020SSam Ravnborg #define Q40_LED_ON() master_outb(1,LED_REG) 2349148020SSam Ravnborg #define Q40_LED_OFF() master_outb(0,LED_REG) 2449148020SSam Ravnborg 2549148020SSam Ravnborg #define INTERRUPT_REG IIRQ_REG /* "native" ints */ 2649148020SSam Ravnborg #define KEY_IRQ_ENABLE_REG 0x08 /**/ 2749148020SSam Ravnborg #define KEYBOARD_UNLOCK_REG 0x20 /* clear kb int */ 2849148020SSam Ravnborg 2949148020SSam Ravnborg #define SAMPLE_ENABLE_REG 0x14 /* generate SAMPLE ints */ 3049148020SSam Ravnborg #define SAMPLE_RATE_REG 0x2c 3149148020SSam Ravnborg #define SAMPLE_CLEAR_REG 0x28 3249148020SSam Ravnborg #define SAMPLE_LOW 0x00 3349148020SSam Ravnborg #define SAMPLE_HIGH 0x01 3449148020SSam Ravnborg 3549148020SSam Ravnborg #define FRAME_RATE_REG 0x38 /* generate FRAME ints at 200 HZ rate */ 3649148020SSam Ravnborg 3749148020SSam Ravnborg #if 0 3849148020SSam Ravnborg #define SER_ENABLE_REG 0x0c /* allow serial ints to be generated */ 3949148020SSam Ravnborg #endif 4049148020SSam Ravnborg #define EXT_ENABLE_REG 0x10 /* ... rest of the ISA ints ... */ 4149148020SSam Ravnborg 4249148020SSam Ravnborg 4349148020SSam Ravnborg #define master_inb(_reg_) in_8((unsigned char *)q40_master_addr+_reg_) 4449148020SSam Ravnborg #define master_outb(_b_,_reg_) out_8((unsigned char *)q40_master_addr+_reg_,_b_) 4549148020SSam Ravnborg 4649148020SSam Ravnborg /* RTC defines */ 4749148020SSam Ravnborg 4849148020SSam Ravnborg #define Q40_RTC_BASE (0xff021ffc) 4949148020SSam Ravnborg 5049148020SSam Ravnborg #define Q40_RTC_YEAR (*(volatile unsigned char *)(Q40_RTC_BASE+0)) 5149148020SSam Ravnborg #define Q40_RTC_MNTH (*(volatile unsigned char *)(Q40_RTC_BASE-4)) 5249148020SSam Ravnborg #define Q40_RTC_DATE (*(volatile unsigned char *)(Q40_RTC_BASE-8)) 5349148020SSam Ravnborg #define Q40_RTC_DOW (*(volatile unsigned char *)(Q40_RTC_BASE-12)) 5449148020SSam Ravnborg #define Q40_RTC_HOUR (*(volatile unsigned char *)(Q40_RTC_BASE-16)) 5549148020SSam Ravnborg #define Q40_RTC_MINS (*(volatile unsigned char *)(Q40_RTC_BASE-20)) 5649148020SSam Ravnborg #define Q40_RTC_SECS (*(volatile unsigned char *)(Q40_RTC_BASE-24)) 5749148020SSam Ravnborg #define Q40_RTC_CTRL (*(volatile unsigned char *)(Q40_RTC_BASE-28)) 5849148020SSam Ravnborg 5949148020SSam Ravnborg /* some control bits */ 6049148020SSam Ravnborg #define Q40_RTC_READ 64 /* prepare for reading */ 6149148020SSam Ravnborg #define Q40_RTC_WRITE 128 6249148020SSam Ravnborg 6349148020SSam Ravnborg /* define some Q40 specific ints */ 64a1ce3928SDavid Howells #include <asm/q40ints.h> 6549148020SSam Ravnborg 6649148020SSam Ravnborg /* misc defs */ 6749148020SSam Ravnborg #define DAC_LEFT ((unsigned char *)0xff008000) 6849148020SSam Ravnborg #define DAC_RIGHT ((unsigned char *)0xff008004) 6949148020SSam Ravnborg 7049148020SSam Ravnborg #endif /* _Q40_MASTER_H */ 71