1 #ifndef _M68K_PGTABLE_H 2 #define _M68K_PGTABLE_H 3 4 #include <asm-generic/4level-fixup.h> 5 6 #include <asm/setup.h> 7 8 #ifndef __ASSEMBLY__ 9 #include <asm/processor.h> 10 #include <linux/sched.h> 11 #include <linux/threads.h> 12 13 /* 14 * This file contains the functions and defines necessary to modify and use 15 * the m68k page table tree. 16 */ 17 18 #include <asm/virtconvert.h> 19 20 /* Certain architectures need to do special things when pte's 21 * within a page table are directly modified. Thus, the following 22 * hook is made available. 23 */ 24 #define set_pte(pteptr, pteval) \ 25 do{ \ 26 *(pteptr) = (pteval); \ 27 } while(0) 28 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) 29 30 31 /* PMD_SHIFT determines the size of the area a second-level page table can map */ 32 #ifdef CONFIG_SUN3 33 #define PMD_SHIFT 17 34 #else 35 #define PMD_SHIFT 22 36 #endif 37 #define PMD_SIZE (1UL << PMD_SHIFT) 38 #define PMD_MASK (~(PMD_SIZE-1)) 39 40 /* PGDIR_SHIFT determines what a third-level page table entry can map */ 41 #ifdef CONFIG_SUN3 42 #define PGDIR_SHIFT 17 43 #elif defined(CONFIG_COLDFIRE) 44 #define PGDIR_SHIFT 22 45 #else 46 #define PGDIR_SHIFT 25 47 #endif 48 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 49 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 50 51 /* 52 * entries per page directory level: the m68k is configured as three-level, 53 * so we do have PMD level physically. 54 */ 55 #ifdef CONFIG_SUN3 56 #define PTRS_PER_PTE 16 57 #define __PAGETABLE_PMD_FOLDED 58 #define PTRS_PER_PMD 1 59 #define PTRS_PER_PGD 2048 60 #elif defined(CONFIG_COLDFIRE) 61 #define PTRS_PER_PTE 512 62 #define __PAGETABLE_PMD_FOLDED 63 #define PTRS_PER_PMD 1 64 #define PTRS_PER_PGD 1024 65 #else 66 #define PTRS_PER_PTE 1024 67 #define PTRS_PER_PMD 8 68 #define PTRS_PER_PGD 128 69 #endif 70 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) 71 #define FIRST_USER_ADDRESS 0UL 72 73 /* Virtual address region for use by kernel_map() */ 74 #ifdef CONFIG_SUN3 75 #define KMAP_START 0x0DC00000 76 #define KMAP_END 0x0E000000 77 #elif defined(CONFIG_COLDFIRE) 78 #define KMAP_START 0xe0000000 79 #define KMAP_END 0xf0000000 80 #else 81 #define KMAP_START 0xd0000000 82 #define KMAP_END 0xf0000000 83 #endif 84 85 #ifdef CONFIG_SUN3 86 extern unsigned long m68k_vmalloc_end; 87 #define VMALLOC_START 0x0f800000 88 #define VMALLOC_END m68k_vmalloc_end 89 #elif defined(CONFIG_COLDFIRE) 90 #define VMALLOC_START 0xd0000000 91 #define VMALLOC_END 0xe0000000 92 #else 93 /* Just any arbitrary offset to the start of the vmalloc VM area: the 94 * current 8MB value just means that there will be a 8MB "hole" after the 95 * physical memory until the kernel virtual memory starts. That means that 96 * any out-of-bounds memory accesses will hopefully be caught. 97 * The vmalloc() routines leaves a hole of 4kB between each vmalloced 98 * area for the same reason. ;) 99 */ 100 #define VMALLOC_OFFSET (8*1024*1024) 101 #define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) 102 #define VMALLOC_END KMAP_START 103 #endif 104 105 /* zero page used for uninitialized stuff */ 106 extern void *empty_zero_page; 107 108 /* 109 * ZERO_PAGE is a global shared page that is always zero: used 110 * for zero-mapped memory areas etc.. 111 */ 112 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 113 114 /* number of bits that fit into a memory pointer */ 115 #define BITS_PER_PTR (8*sizeof(unsigned long)) 116 117 /* to align the pointer to a pointer address */ 118 #define PTR_MASK (~(sizeof(void*)-1)) 119 120 /* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */ 121 /* 64-bit machines, beware! SRB. */ 122 #define SIZEOF_PTR_LOG2 2 123 124 extern void kernel_set_cachemode(void *addr, unsigned long size, int cmode); 125 126 /* 127 * The m68k doesn't have any external MMU info: the kernel page 128 * tables contain all the necessary information. The Sun3 does, but 129 * they are updated on demand. 130 */ 131 static inline void update_mmu_cache(struct vm_area_struct *vma, 132 unsigned long address, pte_t *ptep) 133 { 134 } 135 136 #endif /* !__ASSEMBLY__ */ 137 138 #define kern_addr_valid(addr) (1) 139 140 /* MMU-specific headers */ 141 142 #ifdef CONFIG_SUN3 143 #include <asm/sun3_pgtable.h> 144 #elif defined(CONFIG_COLDFIRE) 145 #include <asm/mcf_pgtable.h> 146 #else 147 #include <asm/motorola_pgtable.h> 148 #endif 149 150 #ifndef __ASSEMBLY__ 151 /* 152 * Macro to mark a page protection value as "uncacheable". 153 */ 154 #ifdef CONFIG_COLDFIRE 155 # define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | CF_PAGE_NOCACHE)) 156 #else 157 #ifdef SUN3_PAGE_NOCACHE 158 # define __SUN3_PAGE_NOCACHE SUN3_PAGE_NOCACHE 159 #else 160 # define __SUN3_PAGE_NOCACHE 0 161 #endif 162 #define pgprot_noncached(prot) \ 163 (MMU_IS_SUN3 \ 164 ? (__pgprot(pgprot_val(prot) | __SUN3_PAGE_NOCACHE)) \ 165 : ((MMU_IS_851 || MMU_IS_030) \ 166 ? (__pgprot(pgprot_val(prot) | _PAGE_NOCACHE030)) \ 167 : (MMU_IS_040 || MMU_IS_060) \ 168 ? (__pgprot((pgprot_val(prot) & _CACHEMASK040) | _PAGE_NOCACHE_S)) \ 169 : (prot))) 170 171 #endif /* CONFIG_COLDFIRE */ 172 #include <asm-generic/pgtable.h> 173 #endif /* !__ASSEMBLY__ */ 174 175 /* 176 * No page table caches to initialise 177 */ 178 #define pgtable_cache_init() do { } while (0) 179 180 #define check_pgt_cache() do { } while (0) 181 182 #endif /* _M68K_PGTABLE_H */ 183