xref: /openbmc/linux/arch/m68k/include/asm/mvme16xhw.h (revision 9cfc5c90)
1 #ifndef _M68K_MVME16xHW_H_
2 #define _M68K_MVME16xHW_H_
3 
4 #include <asm/irq.h>
5 
6 
7 typedef struct {
8 	u_char	ack_icr,
9 		flt_icr,
10 		sel_icr,
11 		pe_icr,
12 		bsy_icr,
13 		spare1,
14 		isr,
15 		cr,
16 		spare2,
17 		spare3,
18 		spare4,
19 		data;
20 } MVMElp, *MVMElpPtr;
21 
22 #define MVME_LPR_BASE	0xfff42030
23 
24 #define mvmelp   ((*(volatile MVMElpPtr)(MVME_LPR_BASE)))
25 
26 typedef struct {
27 	unsigned char
28 		ctrl,
29 		bcd_sec,
30 		bcd_min,
31 		bcd_hr,
32 		bcd_dow,
33 		bcd_dom,
34 		bcd_mth,
35 		bcd_year;
36 } MK48T08_t, *MK48T08ptr_t;
37 
38 #define RTC_WRITE	0x80
39 #define RTC_READ	0x40
40 #define RTC_STOP	0x20
41 
42 #define MVME_RTC_BASE	0xfffc1ff8
43 
44 #define MVME_I596_BASE	0xfff46000
45 
46 #define MVME_SCC_A_ADDR	0xfff45005
47 #define MVME_SCC_B_ADDR	0xfff45001
48 #define MVME_SCC_PCLK	10000000
49 
50 #define MVME162_IRQ_TYPE_PRIO	0
51 
52 #define MVME167_IRQ_PRN		(IRQ_USER+20)
53 #define MVME16x_IRQ_I596	(IRQ_USER+23)
54 #define MVME16x_IRQ_SCSI	(IRQ_USER+21)
55 #define MVME16x_IRQ_FLY		(IRQ_USER+63)
56 #define MVME167_IRQ_SER_ERR	(IRQ_USER+28)
57 #define MVME167_IRQ_SER_MODEM	(IRQ_USER+29)
58 #define MVME167_IRQ_SER_TX	(IRQ_USER+30)
59 #define MVME167_IRQ_SER_RX	(IRQ_USER+31)
60 #define MVME16x_IRQ_TIMER	(IRQ_USER+25)
61 #define MVME167_IRQ_ABORT	(IRQ_USER+46)
62 #define MVME162_IRQ_ABORT	(IRQ_USER+30)
63 
64 /* SCC interrupts, for MVME162 */
65 #define MVME162_IRQ_SCC_BASE		(IRQ_USER+0)
66 #define MVME162_IRQ_SCCB_TX		(IRQ_USER+0)
67 #define MVME162_IRQ_SCCB_STAT		(IRQ_USER+2)
68 #define MVME162_IRQ_SCCB_RX		(IRQ_USER+4)
69 #define MVME162_IRQ_SCCB_SPCOND		(IRQ_USER+6)
70 #define MVME162_IRQ_SCCA_TX		(IRQ_USER+8)
71 #define MVME162_IRQ_SCCA_STAT		(IRQ_USER+10)
72 #define MVME162_IRQ_SCCA_RX		(IRQ_USER+12)
73 #define MVME162_IRQ_SCCA_SPCOND		(IRQ_USER+14)
74 
75 /* MVME162 version register */
76 
77 #define MVME162_VERSION_REG	0xfff4202e
78 
79 extern unsigned short mvme16x_config;
80 
81 /* Lower 8 bits must match the revision register in the MC2 chip */
82 
83 #define MVME16x_CONFIG_SPEED_32		0x0001
84 #define MVME16x_CONFIG_NO_VMECHIP2	0x0002
85 #define MVME16x_CONFIG_NO_SCSICHIP	0x0004
86 #define MVME16x_CONFIG_NO_ETHERNET	0x0008
87 #define MVME16x_CONFIG_GOT_FPU		0x0010
88 
89 #define MVME16x_CONFIG_GOT_LP		0x0100
90 #define MVME16x_CONFIG_GOT_CD2401	0x0200
91 #define MVME16x_CONFIG_GOT_SCCA		0x0400
92 #define MVME16x_CONFIG_GOT_SCCB		0x0800
93 
94 #endif
95