1 /****************************************************************************/ 2 3 /* 4 * mcfuart.h -- ColdFire internal UART support defines. 5 * 6 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com) 7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com) 8 */ 9 10 /****************************************************************************/ 11 #ifndef mcfuart_h 12 #define mcfuart_h 13 /****************************************************************************/ 14 15 /* 16 * Define the base address of the UARTS within the MBAR address 17 * space. 18 */ 19 #if defined(CONFIG_M5272) 20 #define MCFUART_BASE1 0x100 /* Base address of UART1 */ 21 #define MCFUART_BASE2 0x140 /* Base address of UART2 */ 22 #elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) 23 #if defined(CONFIG_NETtel) 24 #define MCFUART_BASE1 0x180 /* Base address of UART1 */ 25 #define MCFUART_BASE2 0x140 /* Base address of UART2 */ 26 #else 27 #define MCFUART_BASE1 0x140 /* Base address of UART1 */ 28 #define MCFUART_BASE2 0x180 /* Base address of UART2 */ 29 #endif 30 #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) 31 #define MCFUART_BASE1 0x200 /* Base address of UART1 */ 32 #define MCFUART_BASE2 0x240 /* Base address of UART2 */ 33 #define MCFUART_BASE3 0x280 /* Base address of UART3 */ 34 #elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) 35 #if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) 36 #define MCFUART_BASE1 0x200 /* Base address of UART1 */ 37 #define MCFUART_BASE2 0x1c0 /* Base address of UART2 */ 38 #else 39 #define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ 40 #define MCFUART_BASE2 0x200 /* Base address of UART2 */ 41 #endif 42 #elif defined(CONFIG_M520x) 43 #define MCFUART_BASE1 0x60000 /* Base address of UART1 */ 44 #define MCFUART_BASE2 0x64000 /* Base address of UART2 */ 45 #define MCFUART_BASE3 0x68000 /* Base address of UART2 */ 46 #elif defined(CONFIG_M532x) 47 #define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */ 48 #define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */ 49 #define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */ 50 #endif 51 52 53 #include <linux/serial_core.h> 54 #include <linux/platform_device.h> 55 56 struct mcf_platform_uart { 57 unsigned long mapbase; /* Physical address base */ 58 void __iomem *membase; /* Virtual address if mapped */ 59 unsigned int irq; /* Interrupt vector */ 60 unsigned int uartclk; /* UART clock rate */ 61 }; 62 63 /* 64 * Define the ColdFire UART register set addresses. 65 */ 66 #define MCFUART_UMR 0x00 /* Mode register (r/w) */ 67 #define MCFUART_USR 0x04 /* Status register (r) */ 68 #define MCFUART_UCSR 0x04 /* Clock Select (w) */ 69 #define MCFUART_UCR 0x08 /* Command register (w) */ 70 #define MCFUART_URB 0x0c /* Receiver Buffer (r) */ 71 #define MCFUART_UTB 0x0c /* Transmit Buffer (w) */ 72 #define MCFUART_UIPCR 0x10 /* Input Port Change (r) */ 73 #define MCFUART_UACR 0x10 /* Auxiliary Control (w) */ 74 #define MCFUART_UISR 0x14 /* Interrupt Status (r) */ 75 #define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */ 76 #define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */ 77 #define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */ 78 #ifdef CONFIG_M5272 79 #define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */ 80 #define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */ 81 #define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ 82 #else 83 #define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ 84 #endif 85 #define MCFUART_UIPR 0x34 /* Input Port (r) */ 86 #define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */ 87 #define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */ 88 89 90 /* 91 * Define bit flags in Mode Register 1 (MR1). 92 */ 93 #define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */ 94 #define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */ 95 #define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */ 96 #define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */ 97 #define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */ 98 99 #define MCFUART_MR1_PARITYNONE 0x10 /* No parity */ 100 #define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */ 101 #define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */ 102 #define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */ 103 #define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */ 104 105 #define MCFUART_MR1_CS5 0x00 /* 5 bits per char */ 106 #define MCFUART_MR1_CS6 0x01 /* 6 bits per char */ 107 #define MCFUART_MR1_CS7 0x02 /* 7 bits per char */ 108 #define MCFUART_MR1_CS8 0x03 /* 8 bits per char */ 109 110 /* 111 * Define bit flags in Mode Register 2 (MR2). 112 */ 113 #define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */ 114 #define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */ 115 #define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */ 116 #define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */ 117 #define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */ 118 119 #define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */ 120 #define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */ 121 #define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */ 122 123 /* 124 * Define bit flags in Status Register (USR). 125 */ 126 #define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */ 127 #define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */ 128 #define MCFUART_USR_RXPARITY 0x20 /* Received parity error */ 129 #define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */ 130 #define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */ 131 #define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */ 132 #define MCFUART_USR_RXFULL 0x02 /* Receiver full */ 133 #define MCFUART_USR_RXREADY 0x01 /* Receiver ready */ 134 135 #define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \ 136 MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN) 137 138 /* 139 * Define bit flags in Clock Select Register (UCSR). 140 */ 141 #define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */ 142 #define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */ 143 #define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */ 144 145 #define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */ 146 #define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */ 147 #define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */ 148 149 /* 150 * Define bit flags in Command Register (UCR). 151 */ 152 #define MCFUART_UCR_CMDNULL 0x00 /* No command */ 153 #define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */ 154 #define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */ 155 #define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */ 156 #define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */ 157 #define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */ 158 #define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */ 159 #define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */ 160 161 #define MCFUART_UCR_TXNULL 0x00 /* No TX command */ 162 #define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */ 163 #define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */ 164 #define MCFUART_UCR_RXNULL 0x00 /* No RX command */ 165 #define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */ 166 #define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */ 167 168 /* 169 * Define bit flags in Input Port Change Register (UIPCR). 170 */ 171 #define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */ 172 #define MCFUART_UIPCR_CTS 0x01 /* CTS value */ 173 174 /* 175 * Define bit flags in Input Port Register (UIP). 176 */ 177 #define MCFUART_UIPR_CTS 0x01 /* CTS value */ 178 179 /* 180 * Define bit flags in Output Port Registers (UOP). 181 * Clear bit by writing to UOP0, set by writing to UOP1. 182 */ 183 #define MCFUART_UOP_RTS 0x01 /* RTS set or clear */ 184 185 /* 186 * Define bit flags in the Auxiliary Control Register (UACR). 187 */ 188 #define MCFUART_UACR_IEC 0x01 /* Input enable control */ 189 190 /* 191 * Define bit flags in Interrupt Status Register (UISR). 192 * These same bits are used for the Interrupt Mask Register (UIMR). 193 */ 194 #define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */ 195 #define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */ 196 #define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */ 197 #define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */ 198 199 #ifdef CONFIG_M5272 200 /* 201 * Define bit flags in the Transmitter FIFO Register (UTF). 202 */ 203 #define MCFUART_UTF_TXB 0x1f /* Transmitter data level */ 204 #define MCFUART_UTF_FULL 0x20 /* Transmitter fifo full */ 205 #define MCFUART_UTF_TXS 0xc0 /* Transmitter status */ 206 207 /* 208 * Define bit flags in the Receiver FIFO Register (URF). 209 */ 210 #define MCFUART_URF_RXB 0x1f /* Receiver data level */ 211 #define MCFUART_URF_FULL 0x20 /* Receiver fifo full */ 212 #define MCFUART_URF_RXS 0xc0 /* Receiver status */ 213 #endif 214 215 /****************************************************************************/ 216 #endif /* mcfuart_h */ 217