1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 249148020SSam Ravnborg /****************************************************************************/ 349148020SSam Ravnborg 449148020SSam Ravnborg /* 549148020SSam Ravnborg * mcfuart.h -- ColdFire internal UART support defines. 649148020SSam Ravnborg * 749148020SSam Ravnborg * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com) 849148020SSam Ravnborg * (C) Copyright 2000, Lineo Inc. (www.lineo.com) 949148020SSam Ravnborg */ 1049148020SSam Ravnborg 1149148020SSam Ravnborg /****************************************************************************/ 1249148020SSam Ravnborg #ifndef mcfuart_h 1349148020SSam Ravnborg #define mcfuart_h 1449148020SSam Ravnborg /****************************************************************************/ 1549148020SSam Ravnborg 1649148020SSam Ravnborg #include <linux/serial_core.h> 1749148020SSam Ravnborg #include <linux/platform_device.h> 1849148020SSam Ravnborg 1949148020SSam Ravnborg struct mcf_platform_uart { 2049148020SSam Ravnborg unsigned long mapbase; /* Physical address base */ 2149148020SSam Ravnborg void __iomem *membase; /* Virtual address if mapped */ 2249148020SSam Ravnborg unsigned int irq; /* Interrupt vector */ 2349148020SSam Ravnborg unsigned int uartclk; /* UART clock rate */ 2449148020SSam Ravnborg }; 2549148020SSam Ravnborg 2649148020SSam Ravnborg /* 2749148020SSam Ravnborg * Define the ColdFire UART register set addresses. 2849148020SSam Ravnborg */ 2949148020SSam Ravnborg #define MCFUART_UMR 0x00 /* Mode register (r/w) */ 3049148020SSam Ravnborg #define MCFUART_USR 0x04 /* Status register (r) */ 3149148020SSam Ravnborg #define MCFUART_UCSR 0x04 /* Clock Select (w) */ 3249148020SSam Ravnborg #define MCFUART_UCR 0x08 /* Command register (w) */ 3349148020SSam Ravnborg #define MCFUART_URB 0x0c /* Receiver Buffer (r) */ 3449148020SSam Ravnborg #define MCFUART_UTB 0x0c /* Transmit Buffer (w) */ 3549148020SSam Ravnborg #define MCFUART_UIPCR 0x10 /* Input Port Change (r) */ 3649148020SSam Ravnborg #define MCFUART_UACR 0x10 /* Auxiliary Control (w) */ 3749148020SSam Ravnborg #define MCFUART_UISR 0x14 /* Interrupt Status (r) */ 3849148020SSam Ravnborg #define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */ 3949148020SSam Ravnborg #define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */ 4049148020SSam Ravnborg #define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */ 4149148020SSam Ravnborg #ifdef CONFIG_M5272 4249148020SSam Ravnborg #define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */ 4349148020SSam Ravnborg #define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */ 4449148020SSam Ravnborg #define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ 4555148f6fSGreg Ungerer #endif 4655148f6fSGreg Ungerer #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ 4704e037aaSSteven King defined(CONFIG_M5249) || defined(CONFIG_M525x) || \ 4804e037aaSSteven King defined(CONFIG_M5307) || defined(CONFIG_M5407) 4949148020SSam Ravnborg #define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ 5049148020SSam Ravnborg #endif 5149148020SSam Ravnborg #define MCFUART_UIPR 0x34 /* Input Port (r) */ 5249148020SSam Ravnborg #define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */ 5349148020SSam Ravnborg #define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */ 5449148020SSam Ravnborg 5549148020SSam Ravnborg 5649148020SSam Ravnborg /* 5749148020SSam Ravnborg * Define bit flags in Mode Register 1 (MR1). 5849148020SSam Ravnborg */ 5949148020SSam Ravnborg #define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */ 6049148020SSam Ravnborg #define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */ 6149148020SSam Ravnborg #define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */ 6249148020SSam Ravnborg #define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */ 6349148020SSam Ravnborg #define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */ 6449148020SSam Ravnborg 6549148020SSam Ravnborg #define MCFUART_MR1_PARITYNONE 0x10 /* No parity */ 6649148020SSam Ravnborg #define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */ 6749148020SSam Ravnborg #define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */ 6849148020SSam Ravnborg #define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */ 6949148020SSam Ravnborg #define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */ 7049148020SSam Ravnborg 7149148020SSam Ravnborg #define MCFUART_MR1_CS5 0x00 /* 5 bits per char */ 7249148020SSam Ravnborg #define MCFUART_MR1_CS6 0x01 /* 6 bits per char */ 7349148020SSam Ravnborg #define MCFUART_MR1_CS7 0x02 /* 7 bits per char */ 7449148020SSam Ravnborg #define MCFUART_MR1_CS8 0x03 /* 8 bits per char */ 7549148020SSam Ravnborg 7649148020SSam Ravnborg /* 7749148020SSam Ravnborg * Define bit flags in Mode Register 2 (MR2). 7849148020SSam Ravnborg */ 7949148020SSam Ravnborg #define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */ 8049148020SSam Ravnborg #define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */ 8149148020SSam Ravnborg #define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */ 8249148020SSam Ravnborg #define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */ 8349148020SSam Ravnborg #define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */ 8449148020SSam Ravnborg 8549148020SSam Ravnborg #define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */ 8649148020SSam Ravnborg #define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */ 8749148020SSam Ravnborg #define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */ 8849148020SSam Ravnborg 8949148020SSam Ravnborg /* 9049148020SSam Ravnborg * Define bit flags in Status Register (USR). 9149148020SSam Ravnborg */ 9249148020SSam Ravnborg #define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */ 9349148020SSam Ravnborg #define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */ 9449148020SSam Ravnborg #define MCFUART_USR_RXPARITY 0x20 /* Received parity error */ 9549148020SSam Ravnborg #define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */ 9649148020SSam Ravnborg #define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */ 9749148020SSam Ravnborg #define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */ 9849148020SSam Ravnborg #define MCFUART_USR_RXFULL 0x02 /* Receiver full */ 9949148020SSam Ravnborg #define MCFUART_USR_RXREADY 0x01 /* Receiver ready */ 10049148020SSam Ravnborg 10149148020SSam Ravnborg #define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \ 10249148020SSam Ravnborg MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN) 10349148020SSam Ravnborg 10449148020SSam Ravnborg /* 10549148020SSam Ravnborg * Define bit flags in Clock Select Register (UCSR). 10649148020SSam Ravnborg */ 10749148020SSam Ravnborg #define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */ 10849148020SSam Ravnborg #define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */ 10949148020SSam Ravnborg #define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */ 11049148020SSam Ravnborg 11149148020SSam Ravnborg #define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */ 11249148020SSam Ravnborg #define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */ 11349148020SSam Ravnborg #define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */ 11449148020SSam Ravnborg 11549148020SSam Ravnborg /* 11649148020SSam Ravnborg * Define bit flags in Command Register (UCR). 11749148020SSam Ravnborg */ 11849148020SSam Ravnborg #define MCFUART_UCR_CMDNULL 0x00 /* No command */ 11949148020SSam Ravnborg #define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */ 12049148020SSam Ravnborg #define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */ 12149148020SSam Ravnborg #define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */ 12249148020SSam Ravnborg #define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */ 12349148020SSam Ravnborg #define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */ 12449148020SSam Ravnborg #define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */ 12549148020SSam Ravnborg #define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */ 12649148020SSam Ravnborg 12749148020SSam Ravnborg #define MCFUART_UCR_TXNULL 0x00 /* No TX command */ 12849148020SSam Ravnborg #define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */ 12949148020SSam Ravnborg #define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */ 13049148020SSam Ravnborg #define MCFUART_UCR_RXNULL 0x00 /* No RX command */ 13149148020SSam Ravnborg #define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */ 13249148020SSam Ravnborg #define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */ 13349148020SSam Ravnborg 13449148020SSam Ravnborg /* 13549148020SSam Ravnborg * Define bit flags in Input Port Change Register (UIPCR). 13649148020SSam Ravnborg */ 13749148020SSam Ravnborg #define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */ 13849148020SSam Ravnborg #define MCFUART_UIPCR_CTS 0x01 /* CTS value */ 13949148020SSam Ravnborg 14049148020SSam Ravnborg /* 14149148020SSam Ravnborg * Define bit flags in Input Port Register (UIP). 14249148020SSam Ravnborg */ 14349148020SSam Ravnborg #define MCFUART_UIPR_CTS 0x01 /* CTS value */ 14449148020SSam Ravnborg 14549148020SSam Ravnborg /* 14649148020SSam Ravnborg * Define bit flags in Output Port Registers (UOP). 14749148020SSam Ravnborg * Clear bit by writing to UOP0, set by writing to UOP1. 14849148020SSam Ravnborg */ 14949148020SSam Ravnborg #define MCFUART_UOP_RTS 0x01 /* RTS set or clear */ 15049148020SSam Ravnborg 15149148020SSam Ravnborg /* 15249148020SSam Ravnborg * Define bit flags in the Auxiliary Control Register (UACR). 15349148020SSam Ravnborg */ 15449148020SSam Ravnborg #define MCFUART_UACR_IEC 0x01 /* Input enable control */ 15549148020SSam Ravnborg 15649148020SSam Ravnborg /* 15749148020SSam Ravnborg * Define bit flags in Interrupt Status Register (UISR). 15849148020SSam Ravnborg * These same bits are used for the Interrupt Mask Register (UIMR). 15949148020SSam Ravnborg */ 16049148020SSam Ravnborg #define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */ 16149148020SSam Ravnborg #define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */ 16249148020SSam Ravnborg #define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */ 16349148020SSam Ravnborg #define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */ 16449148020SSam Ravnborg 16549148020SSam Ravnborg #ifdef CONFIG_M5272 16649148020SSam Ravnborg /* 16749148020SSam Ravnborg * Define bit flags in the Transmitter FIFO Register (UTF). 16849148020SSam Ravnborg */ 16949148020SSam Ravnborg #define MCFUART_UTF_TXB 0x1f /* Transmitter data level */ 17049148020SSam Ravnborg #define MCFUART_UTF_FULL 0x20 /* Transmitter fifo full */ 17149148020SSam Ravnborg #define MCFUART_UTF_TXS 0xc0 /* Transmitter status */ 17249148020SSam Ravnborg 17349148020SSam Ravnborg /* 17449148020SSam Ravnborg * Define bit flags in the Receiver FIFO Register (URF). 17549148020SSam Ravnborg */ 17649148020SSam Ravnborg #define MCFUART_URF_RXB 0x1f /* Receiver data level */ 17749148020SSam Ravnborg #define MCFUART_URF_FULL 0x20 /* Receiver fifo full */ 17849148020SSam Ravnborg #define MCFUART_URF_RXS 0xc0 /* Receiver status */ 17949148020SSam Ravnborg #endif 18049148020SSam Ravnborg 1815b2e6555SGreg Ungerer #if defined(CONFIG_M54xx) 18248a232d1SPhilippe De Muyter #define MCFUART_TXFIFOSIZE 512 18348a232d1SPhilippe De Muyter #elif defined(CONFIG_M5272) 1843732b68fSPhilippe De Muyter #define MCFUART_TXFIFOSIZE 25 1853732b68fSPhilippe De Muyter #else 1863732b68fSPhilippe De Muyter #define MCFUART_TXFIFOSIZE 1 1873732b68fSPhilippe De Muyter #endif 18849148020SSam Ravnborg /****************************************************************************/ 18949148020SSam Ravnborg #endif /* mcfuart_h */ 190