1 /****************************************************************************/ 2 3 /* 4 * mcftimer.h -- ColdFire internal TIMER support defines. 5 * 6 * (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com> 7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com) 8 */ 9 10 /****************************************************************************/ 11 #ifndef mcftimer_h 12 #define mcftimer_h 13 /****************************************************************************/ 14 15 /* 16 * Define the TIMER register set addresses. 17 */ 18 #define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */ 19 #define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */ 20 #define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */ 21 #define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */ 22 #if defined(CONFIG_M53xx) || defined(CONFIG_M5441x) 23 #define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */ 24 #else 25 #define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ 26 #endif 27 28 /* 29 * Bit definitions for the Timer Mode Register (TMR). 30 * Register bit flags are common across ColdFires. 31 */ 32 #define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ 33 #define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ 34 #define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */ 35 #define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */ 36 #define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */ 37 #define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */ 38 #define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */ 39 #define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */ 40 #define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */ 41 #define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */ 42 #define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */ 43 #define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */ 44 #define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */ 45 #define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */ 46 #define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */ 47 #define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */ 48 #define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */ 49 50 /* 51 * Bit definitions for the Timer Event Registers (TER). 52 */ 53 #define MCFTIMER_TER_CAP 0x01 /* Capture event */ 54 #define MCFTIMER_TER_REF 0x02 /* Reference event */ 55 56 /****************************************************************************/ 57 #endif /* mcftimer_h */ 58