1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 249148020SSam Ravnborg /****************************************************************************/ 349148020SSam Ravnborg 449148020SSam Ravnborg /* 549148020SSam Ravnborg * mcftimer.h -- ColdFire internal TIMER support defines. 649148020SSam Ravnborg * 749148020SSam Ravnborg * (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com> 849148020SSam Ravnborg * (C) Copyright 2000, Lineo Inc. (www.lineo.com) 949148020SSam Ravnborg */ 1049148020SSam Ravnborg 1149148020SSam Ravnborg /****************************************************************************/ 1249148020SSam Ravnborg #ifndef mcftimer_h 1349148020SSam Ravnborg #define mcftimer_h 1449148020SSam Ravnborg /****************************************************************************/ 1549148020SSam Ravnborg 1649148020SSam Ravnborg /* 1749148020SSam Ravnborg * Define the TIMER register set addresses. 1849148020SSam Ravnborg */ 1949148020SSam Ravnborg #define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */ 2049148020SSam Ravnborg #define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */ 2149148020SSam Ravnborg #define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */ 2249148020SSam Ravnborg #define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */ 236eac4027SGreg Ungerer #if defined(CONFIG_M53xx) || defined(CONFIG_M5441x) 2449148020SSam Ravnborg #define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */ 2549148020SSam Ravnborg #else 2649148020SSam Ravnborg #define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ 2749148020SSam Ravnborg #endif 2849148020SSam Ravnborg 2949148020SSam Ravnborg /* 3049148020SSam Ravnborg * Bit definitions for the Timer Mode Register (TMR). 3125985edcSLucas De Marchi * Register bit flags are common across ColdFires. 3249148020SSam Ravnborg */ 3349148020SSam Ravnborg #define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ 3449148020SSam Ravnborg #define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ 3549148020SSam Ravnborg #define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */ 3649148020SSam Ravnborg #define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */ 3749148020SSam Ravnborg #define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */ 3849148020SSam Ravnborg #define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */ 3949148020SSam Ravnborg #define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */ 4049148020SSam Ravnborg #define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */ 4149148020SSam Ravnborg #define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */ 4249148020SSam Ravnborg #define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */ 4349148020SSam Ravnborg #define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */ 4449148020SSam Ravnborg #define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */ 4549148020SSam Ravnborg #define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */ 4649148020SSam Ravnborg #define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */ 4749148020SSam Ravnborg #define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */ 4849148020SSam Ravnborg #define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */ 4949148020SSam Ravnborg #define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */ 5049148020SSam Ravnborg 5149148020SSam Ravnborg /* 5249148020SSam Ravnborg * Bit definitions for the Timer Event Registers (TER). 5349148020SSam Ravnborg */ 5449148020SSam Ravnborg #define MCFTIMER_TER_CAP 0x01 /* Capture event */ 55efbec135SAdam Buchbinder #define MCFTIMER_TER_REF 0x02 /* Reference event */ 5649148020SSam Ravnborg 5749148020SSam Ravnborg /****************************************************************************/ 5849148020SSam Ravnborg #endif /* mcftimer_h */ 59