1 /****************************************************************************/ 2 3 /* 4 * mcfsim.h -- ColdFire System Integration Module support. 5 * 6 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com) 7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com) 8 */ 9 10 /****************************************************************************/ 11 #ifndef mcfsim_h 12 #define mcfsim_h 13 /****************************************************************************/ 14 15 16 /* 17 * Include 5204, 5206/e, 5235, 5249, 5270/5271, 5272, 5280/5282, 18 * 5307 or 5407 specific addresses. 19 */ 20 #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) 21 #include <asm/m5206sim.h> 22 #elif defined(CONFIG_M520x) 23 #include <asm/m520xsim.h> 24 #elif defined(CONFIG_M523x) 25 #include <asm/m523xsim.h> 26 #elif defined(CONFIG_M5249) 27 #include <asm/m5249sim.h> 28 #elif defined(CONFIG_M527x) 29 #include <asm/m527xsim.h> 30 #elif defined(CONFIG_M5272) 31 #include <asm/m5272sim.h> 32 #elif defined(CONFIG_M528x) 33 #include <asm/m528xsim.h> 34 #elif defined(CONFIG_M5307) 35 #include <asm/m5307sim.h> 36 #elif defined(CONFIG_M532x) 37 #include <asm/m532xsim.h> 38 #elif defined(CONFIG_M5407) 39 #include <asm/m5407sim.h> 40 #endif 41 42 43 /* 44 * Define the base address of the SIM within the MBAR address space. 45 */ 46 #define MCFSIM_BASE 0x0 /* Base address of SIM */ 47 48 49 /* 50 * Bit definitions for the ICR family of registers. 51 */ 52 #define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ 53 #define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ 54 #define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ 55 #define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ 56 #define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ 57 #define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ 58 #define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ 59 #define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ 60 #define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ 61 62 #define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ 63 #define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ 64 #define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ 65 #define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ 66 67 /* 68 * Bit definitions for the Interrupt Mask register (IMR). 69 */ 70 #define MCFSIM_IMR_EINT1 0x0002 /* External intr # 1 */ 71 #define MCFSIM_IMR_EINT2 0x0004 /* External intr # 2 */ 72 #define MCFSIM_IMR_EINT3 0x0008 /* External intr # 3 */ 73 #define MCFSIM_IMR_EINT4 0x0010 /* External intr # 4 */ 74 #define MCFSIM_IMR_EINT5 0x0020 /* External intr # 5 */ 75 #define MCFSIM_IMR_EINT6 0x0040 /* External intr # 6 */ 76 #define MCFSIM_IMR_EINT7 0x0080 /* External intr # 7 */ 77 78 #define MCFSIM_IMR_SWD 0x0100 /* Software Watchdog intr */ 79 #define MCFSIM_IMR_TIMER1 0x0200 /* TIMER 1 intr */ 80 #define MCFSIM_IMR_TIMER2 0x0400 /* TIMER 2 intr */ 81 #define MCFSIM_IMR_MBUS 0x0800 /* MBUS intr */ 82 #define MCFSIM_IMR_UART1 0x1000 /* UART 1 intr */ 83 #define MCFSIM_IMR_UART2 0x2000 /* UART 2 intr */ 84 85 #if defined(CONFIG_M5206e) 86 #define MCFSIM_IMR_DMA1 0x4000 /* DMA 1 intr */ 87 #define MCFSIM_IMR_DMA2 0x8000 /* DMA 2 intr */ 88 #elif defined(CONFIG_M5249) || defined(CONFIG_M5307) 89 #define MCFSIM_IMR_DMA0 0x4000 /* DMA 0 intr */ 90 #define MCFSIM_IMR_DMA1 0x8000 /* DMA 1 intr */ 91 #define MCFSIM_IMR_DMA2 0x10000 /* DMA 2 intr */ 92 #define MCFSIM_IMR_DMA3 0x20000 /* DMA 3 intr */ 93 #endif 94 95 /* 96 * Mask for all of the SIM devices. Some parts have more or less 97 * SIM devices. This is a catchall for the sandard set. 98 */ 99 #ifndef MCFSIM_IMR_MASKALL 100 #define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */ 101 #endif 102 103 104 #ifndef __ASSEMBLY__ 105 /* 106 * Definition for the interrupt auto-vectoring support. 107 */ 108 extern void mcf_autovector(unsigned int vec); 109 #endif /* __ASSEMBLY__ */ 110 111 /****************************************************************************/ 112 #endif /* mcfsim_h */ 113