1 /****************************************************************************/ 2 3 /* 4 * mcfdma.h -- Coldfire internal DMA support defines. 5 * 6 * (C) Copyright 1999, Rob Scott (rscott@mtrob.ml.org) 7 */ 8 9 /****************************************************************************/ 10 #ifndef mcfdma_h 11 #define mcfdma_h 12 /****************************************************************************/ 13 14 15 /* 16 * Get address specific defines for this Coldfire member. 17 */ 18 #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) 19 #define MCFDMA_BASE0 0x200 /* Base address of DMA 0 */ 20 #define MCFDMA_BASE1 0x240 /* Base address of DMA 1 */ 21 #elif defined(CONFIG_M5272) 22 #define MCFDMA_BASE0 0x0e0 /* Base address of DMA 0 */ 23 #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) 24 /* These are relative to the IPSBAR, not MBAR */ 25 #define MCFDMA_BASE0 0x100 /* Base address of DMA 0 */ 26 #define MCFDMA_BASE1 0x140 /* Base address of DMA 1 */ 27 #define MCFDMA_BASE2 0x180 /* Base address of DMA 2 */ 28 #define MCFDMA_BASE3 0x1C0 /* Base address of DMA 3 */ 29 #elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) 30 #define MCFDMA_BASE0 0x300 /* Base address of DMA 0 */ 31 #define MCFDMA_BASE1 0x340 /* Base address of DMA 1 */ 32 #define MCFDMA_BASE2 0x380 /* Base address of DMA 2 */ 33 #define MCFDMA_BASE3 0x3C0 /* Base address of DMA 3 */ 34 #endif 35 36 37 #if !defined(CONFIG_M5272) 38 39 /* 40 * Define the DMA register set addresses. 41 * Note: these are longword registers, use unsigned long as data type 42 */ 43 #define MCFDMA_SAR 0x00 /* DMA source address (r/w) */ 44 #define MCFDMA_DAR 0x01 /* DMA destination adr (r/w) */ 45 /* these are word registers, use unsigned short data type */ 46 #define MCFDMA_DCR 0x04 /* DMA control reg (r/w) */ 47 #define MCFDMA_BCR 0x06 /* DMA byte count reg (r/w) */ 48 /* these are byte registers, use unsiged char data type */ 49 #define MCFDMA_DSR 0x10 /* DMA status reg (r/w) */ 50 #define MCFDMA_DIVR 0x14 /* DMA interrupt vec (r/w) */ 51 52 /* 53 * Bit definitions for the DMA Control Register (DCR). 54 */ 55 #define MCFDMA_DCR_INT 0x8000 /* Enable completion irq */ 56 #define MCFDMA_DCR_EEXT 0x4000 /* Enable external DMA req */ 57 #define MCFDMA_DCR_CS 0x2000 /* Enable cycle steal */ 58 #define MCFDMA_DCR_AA 0x1000 /* Enable auto alignment */ 59 #define MCFDMA_DCR_BWC_MASK 0x0E00 /* Bandwidth ctl mask */ 60 #define MCFDMA_DCR_BWC_512 0x0200 /* Bandwidth: 512 Bytes */ 61 #define MCFDMA_DCR_BWC_1024 0x0400 /* Bandwidth: 1024 Bytes */ 62 #define MCFDMA_DCR_BWC_2048 0x0600 /* Bandwidth: 2048 Bytes */ 63 #define MCFDMA_DCR_BWC_4096 0x0800 /* Bandwidth: 4096 Bytes */ 64 #define MCFDMA_DCR_BWC_8192 0x0a00 /* Bandwidth: 8192 Bytes */ 65 #define MCFDMA_DCR_BWC_16384 0x0c00 /* Bandwidth: 16384 Bytes */ 66 #define MCFDMA_DCR_BWC_32768 0x0e00 /* Bandwidth: 32768 Bytes */ 67 #define MCFDMA_DCR_SAA 0x0100 /* Single Address Access */ 68 #define MCFDMA_DCR_S_RW 0x0080 /* SAA read/write value */ 69 #define MCFDMA_DCR_SINC 0x0040 /* Source addr inc enable */ 70 #define MCFDMA_DCR_SSIZE_MASK 0x0030 /* Src xfer size */ 71 #define MCFDMA_DCR_SSIZE_LONG 0x0000 /* Src xfer size, 00 = longw */ 72 #define MCFDMA_DCR_SSIZE_BYTE 0x0010 /* Src xfer size, 01 = byte */ 73 #define MCFDMA_DCR_SSIZE_WORD 0x0020 /* Src xfer size, 10 = word */ 74 #define MCFDMA_DCR_SSIZE_LINE 0x0030 /* Src xfer size, 11 = line */ 75 #define MCFDMA_DCR_DINC 0x0008 /* Dest addr inc enable */ 76 #define MCFDMA_DCR_DSIZE_MASK 0x0006 /* Dest xfer size */ 77 #define MCFDMA_DCR_DSIZE_LONG 0x0000 /* Dest xfer size, 00 = long */ 78 #define MCFDMA_DCR_DSIZE_BYTE 0x0002 /* Dest xfer size, 01 = byte */ 79 #define MCFDMA_DCR_DSIZE_WORD 0x0004 /* Dest xfer size, 10 = word */ 80 #define MCFDMA_DCR_DSIZE_LINE 0x0006 /* Dest xfer size, 11 = line */ 81 #define MCFDMA_DCR_START 0x0001 /* Start transfer */ 82 83 /* 84 * Bit definitions for the DMA Status Register (DSR). 85 */ 86 #define MCFDMA_DSR_CE 0x40 /* Config error */ 87 #define MCFDMA_DSR_BES 0x20 /* Bus Error on source */ 88 #define MCFDMA_DSR_BED 0x10 /* Bus Error on dest */ 89 #define MCFDMA_DSR_REQ 0x04 /* Requests remaining */ 90 #define MCFDMA_DSR_BSY 0x02 /* Busy */ 91 #define MCFDMA_DSR_DONE 0x01 /* DMA transfer complete */ 92 93 #else /* This is an MCF5272 */ 94 95 #define MCFDMA_DMR 0x00 /* Mode Register (r/w) */ 96 #define MCFDMA_DIR 0x03 /* Interrupt trigger register (r/w) */ 97 #define MCFDMA_DSAR 0x03 /* Source Address register (r/w) */ 98 #define MCFDMA_DDAR 0x04 /* Destination Address register (r/w) */ 99 #define MCFDMA_DBCR 0x02 /* Byte Count Register (r/w) */ 100 101 /* Bit definitions for the DMA Mode Register (DMR) */ 102 #define MCFDMA_DMR_RESET 0x80000000L /* Reset bit */ 103 #define MCFDMA_DMR_EN 0x40000000L /* DMA enable */ 104 #define MCFDMA_DMR_RQM 0x000C0000L /* Request Mode Mask */ 105 #define MCFDMA_DMR_RQM_DUAL 0x000C0000L /* Dual address mode, the only valid mode */ 106 #define MCFDMA_DMR_DSTM 0x00002000L /* Destination addressing mask */ 107 #define MCFDMA_DMR_DSTM_SA 0x00000000L /* Destination uses static addressing */ 108 #define MCFDMA_DMR_DSTM_IA 0x00002000L /* Destination uses incremental addressing */ 109 #define MCFDMA_DMR_DSTT_UD 0x00000400L /* Destination is user data */ 110 #define MCFDMA_DMR_DSTT_UC 0x00000800L /* Destination is user code */ 111 #define MCFDMA_DMR_DSTT_SD 0x00001400L /* Destination is supervisor data */ 112 #define MCFDMA_DMR_DSTT_SC 0x00001800L /* Destination is supervisor code */ 113 #define MCFDMA_DMR_DSTS_OFF 0x8 /* offset to the destination size bits */ 114 #define MCFDMA_DMR_DSTS_LONG 0x00000000L /* Long destination size */ 115 #define MCFDMA_DMR_DSTS_BYTE 0x00000100L /* Byte destination size */ 116 #define MCFDMA_DMR_DSTS_WORD 0x00000200L /* Word destination size */ 117 #define MCFDMA_DMR_DSTS_LINE 0x00000300L /* Line destination size */ 118 #define MCFDMA_DMR_SRCM 0x00000020L /* Source addressing mask */ 119 #define MCFDMA_DMR_SRCM_SA 0x00000000L /* Source uses static addressing */ 120 #define MCFDMA_DMR_SRCM_IA 0x00000020L /* Source uses incremental addressing */ 121 #define MCFDMA_DMR_SRCT_UD 0x00000004L /* Source is user data */ 122 #define MCFDMA_DMR_SRCT_UC 0x00000008L /* Source is user code */ 123 #define MCFDMA_DMR_SRCT_SD 0x00000014L /* Source is supervisor data */ 124 #define MCFDMA_DMR_SRCT_SC 0x00000018L /* Source is supervisor code */ 125 #define MCFDMA_DMR_SRCS_OFF 0x0 /* Offset to the source size bits */ 126 #define MCFDMA_DMR_SRCS_LONG 0x00000000L /* Long source size */ 127 #define MCFDMA_DMR_SRCS_BYTE 0x00000001L /* Byte source size */ 128 #define MCFDMA_DMR_SRCS_WORD 0x00000002L /* Word source size */ 129 #define MCFDMA_DMR_SRCS_LINE 0x00000003L /* Line source size */ 130 131 /* Bit definitions for the DMA interrupt register (DIR) */ 132 #define MCFDMA_DIR_INVEN 0x1000 /* Invalid Combination interrupt enable */ 133 #define MCFDMA_DIR_ASCEN 0x0800 /* Address Sequence Complete (Completion) interrupt enable */ 134 #define MCFDMA_DIR_TEEN 0x0200 /* Transfer Error interrupt enable */ 135 #define MCFDMA_DIR_TCEN 0x0100 /* Transfer Complete (a bus transfer, that is) interrupt enable */ 136 #define MCFDMA_DIR_INV 0x0010 /* Invalid Combination */ 137 #define MCFDMA_DIR_ASC 0x0008 /* Address Sequence Complete (DMA Completion) */ 138 #define MCFDMA_DIR_TE 0x0002 /* Transfer Error */ 139 #define MCFDMA_DIR_TC 0x0001 /* Transfer Complete */ 140 141 #endif /* !defined(CONFIG_M5272) */ 142 143 /****************************************************************************/ 144 #endif /* mcfdma_h */ 145