xref: /openbmc/linux/arch/m68k/include/asm/m54xxsim.h (revision e23feb16)
1 /*
2  *	m54xxsim.h -- ColdFire 547x/548x System Integration Unit support.
3  */
4 
5 #ifndef	m54xxsim_h
6 #define m54xxsim_h
7 
8 #define	CPU_NAME		"COLDFIRE(m54xx)"
9 #define	CPU_INSTR_PER_JIFFY	2
10 #define	MCF_BUSCLK		(MCF_CLK / 2)
11 
12 #include <asm/m54xxacr.h>
13 
14 #define MCFINT_VECBASE		64
15 
16 /*
17  *      Interrupt Controller Registers
18  */
19 #define MCFICM_INTC0		(MCF_MBAR + 0x700) 	/* Base for Interrupt Ctrl 0 */
20 
21 #define MCFINTC_IPRH		0x00		/* Interrupt pending 32-63 */
22 #define MCFINTC_IPRL		0x04		/* Interrupt pending 1-31 */
23 #define MCFINTC_IMRH		0x08		/* Interrupt mask 32-63 */
24 #define MCFINTC_IMRL		0x0c		/* Interrupt mask 1-31 */
25 #define MCFINTC_INTFRCH		0x10		/* Interrupt force 32-63 */
26 #define MCFINTC_INTFRCL		0x14		/* Interrupt force 1-31 */
27 #define MCFINTC_IRLR		0x18		/* */
28 #define MCFINTC_IACKL		0x19		/* */
29 #define MCFINTC_ICR0		0x40		/* Base ICR register */
30 
31 /*
32  *	UART module.
33  */
34 #define MCFUART_BASE0		(MCF_MBAR + 0x8600)	/* Base address UART0 */
35 #define MCFUART_BASE1		(MCF_MBAR + 0x8700)	/* Base address UART1 */
36 #define MCFUART_BASE2		(MCF_MBAR + 0x8800)	/* Base address UART2 */
37 #define MCFUART_BASE3		(MCF_MBAR + 0x8900)	/* Base address UART3 */
38 
39 /*
40  *	Define system peripheral IRQ usage.
41  */
42 #define MCF_IRQ_TIMER		(MCFINT_VECBASE + 54)	/* Slice Timer 0 */
43 #define MCF_IRQ_PROFILER	(MCFINT_VECBASE + 53)	/* Slice Timer 1 */
44 #define MCF_IRQ_UART0		(MCFINT_VECBASE + 35)
45 #define MCF_IRQ_UART1		(MCFINT_VECBASE + 34)
46 #define MCF_IRQ_UART2		(MCFINT_VECBASE + 33)
47 #define MCF_IRQ_UART3		(MCFINT_VECBASE + 32)
48 
49 /*
50  *	Slice Timer support.
51  */
52 #define MCFSLT_TIMER0		(MCF_MBAR + 0x900)	/* Base addr TIMER0 */
53 #define MCFSLT_TIMER1		(MCF_MBAR + 0x910)	/* Base addr TIMER1 */
54 
55 /*
56  *	Generic GPIO support
57  */
58 #define MCFGPIO_PIN_MAX		0	/* I am too lazy to count */
59 #define MCFGPIO_IRQ_MAX		-1
60 #define MCFGPIO_IRQ_VECBASE	-1
61 
62 /*
63  *	EDGE Port support.
64  */
65 #define	MCFEPORT_EPPAR		(MCF_MBAR + 0xf00)	/* Pin assignment */
66 #define	MCFEPORT_EPDDR		(MCF_MBAR + 0xf04)	/* Data direction */
67 #define	MCFEPORT_EPIER		(MCF_MBAR + 0xf05)	/* Interrupt enable */
68 #define	MCFEPORT_EPDR		(MCF_MBAR + 0xf08)	/* Port data (w) */
69 #define	MCFEPORT_EPPDR		(MCF_MBAR + 0xf09)	/* Port data (r) */
70 #define	MCFEPORT_EPFR		(MCF_MBAR + 0xf0c)	/* Flags */
71 
72 /*
73  *	Pin Assignment register definitions
74  */
75 #define MCFGPIO_PAR_FBCTL	(MCF_MBAR + 0xA40)
76 #define MCFGPIO_PAR_FBCS	(MCF_MBAR + 0xA42)
77 #define MCFGPIO_PAR_DMA		(MCF_MBAR + 0xA43)
78 #define MCFGPIO_PAR_FECI2CIRQ	(MCF_MBAR + 0xA44)
79 #define MCFGPIO_PAR_PCIBG	(MCF_MBAR + 0xA48)	/* PCI bus grant */
80 #define MCFGPIO_PAR_PCIBR	(MCF_MBAR + 0xA4A)	/* PCI */
81 #define MCFGPIO_PAR_PSC0	(MCF_MBAR + 0xA4F)
82 #define MCFGPIO_PAR_PSC1	(MCF_MBAR + 0xA4E)
83 #define MCFGPIO_PAR_PSC2	(MCF_MBAR + 0xA4D)
84 #define MCFGPIO_PAR_PSC3	(MCF_MBAR + 0xA4C)
85 #define MCFGPIO_PAR_DSPI	(MCF_MBAR + 0xA50)
86 #define MCFGPIO_PAR_TIMER	(MCF_MBAR + 0xA52)
87 
88 #define MCF_PAR_SDA		(0x0008)
89 #define MCF_PAR_SCL		(0x0004)
90 #define MCF_PAR_PSC_TXD		(0x04)
91 #define MCF_PAR_PSC_RXD		(0x08)
92 #define MCF_PAR_PSC_CTS_GPIO	(0x00)
93 #define MCF_PAR_PSC_CTS_BCLK	(0x80)
94 #define MCF_PAR_PSC_CTS_CTS	(0xC0)
95 #define MCF_PAR_PSC_RTS_GPIO    (0x00)
96 #define MCF_PAR_PSC_RTS_FSYNC	(0x20)
97 #define MCF_PAR_PSC_RTS_RTS	(0x30)
98 #define MCF_PAR_PSC_CANRX	(0x40)
99 
100 #endif	/* m54xxsim_h */
101