xref: /openbmc/linux/arch/m68k/include/asm/m54xxsim.h (revision df2634f43f5106947f3735a0b61a6527a4b278cd)
1 /*
2  *	m54xxsim.h -- ColdFire 547x/548x System Integration Unit support.
3  */
4 
5 #ifndef	m54xxsim_h
6 #define m54xxsim_h
7 
8 #define	CPU_NAME		"COLDFIRE(m54xx)"
9 #define	CPU_INSTR_PER_JIFFY	2
10 
11 #include <asm/m54xxacr.h>
12 
13 #define MCFINT_VECBASE		64
14 
15 /*
16  *      Interrupt Controller Registers
17  */
18 #define MCFICM_INTC0		0x0700		/* Base for Interrupt Ctrl 0 */
19 #define MCFINTC_IPRH		0x00		/* Interrupt pending 32-63 */
20 #define MCFINTC_IPRL		0x04		/* Interrupt pending 1-31 */
21 #define MCFINTC_IMRH		0x08		/* Interrupt mask 32-63 */
22 #define MCFINTC_IMRL		0x0c		/* Interrupt mask 1-31 */
23 #define MCFINTC_INTFRCH		0x10		/* Interrupt force 32-63 */
24 #define MCFINTC_INTFRCL		0x14		/* Interrupt force 1-31 */
25 #define MCFINTC_IRLR		0x18		/* */
26 #define MCFINTC_IACKL		0x19		/* */
27 #define MCFINTC_ICR0		0x40		/* Base ICR register */
28 
29 /*
30  *	UART module.
31  */
32 #define MCFUART_BASE1		0x8600		/* Base address of UART1 */
33 #define MCFUART_BASE2		0x8700		/* Base address of UART2 */
34 #define MCFUART_BASE3		0x8800		/* Base address of UART3 */
35 #define MCFUART_BASE4		0x8900		/* Base address of UART4 */
36 
37 /*
38  *	Define system peripheral IRQ usage.
39  */
40 #define MCF_IRQ_TIMER		(64 + 54)	/* Slice Timer 0 */
41 #define MCF_IRQ_PROFILER	(64 + 53)	/* Slice Timer 1 */
42 
43 /*
44  *	Generic GPIO support
45  */
46 #define MCFGPIO_PIN_MAX		0	/* I am too lazy to count */
47 #define MCFGPIO_IRQ_MAX		-1
48 #define MCFGPIO_IRQ_VECBASE	-1
49 
50 /*
51  *	Some PSC related definitions
52  */
53 #define MCF_PAR_PSC(x)		(0x000A4F-((x)&0x3))
54 #define MCF_PAR_SDA		(0x0008)
55 #define MCF_PAR_SCL		(0x0004)
56 #define MCF_PAR_PSC_TXD		(0x04)
57 #define MCF_PAR_PSC_RXD		(0x08)
58 #define MCF_PAR_PSC_RTS(x)	(((x)&0x03)<<4)
59 #define MCF_PAR_PSC_CTS(x)	(((x)&0x03)<<6)
60 #define MCF_PAR_PSC_CTS_GPIO	(0x00)
61 #define MCF_PAR_PSC_CTS_BCLK	(0x80)
62 #define MCF_PAR_PSC_CTS_CTS	(0xC0)
63 #define MCF_PAR_PSC_RTS_GPIO    (0x00)
64 #define MCF_PAR_PSC_RTS_FSYNC	(0x20)
65 #define MCF_PAR_PSC_RTS_RTS	(0x30)
66 #define MCF_PAR_PSC_CANRX	(0x40)
67 
68 #endif	/* m54xxsim_h */
69