1 /* 2 * Bit definitions for the MCF54xx ACR and CACR registers. 3 */ 4 5 #ifndef m54xxacr_h 6 #define m54xxacr_h 7 8 /* 9 * Define the Cache register flags. 10 */ 11 #define CACR_DEC 0x80000000 /* Enable data cache */ 12 #define CACR_DWP 0x40000000 /* Data write protection */ 13 #define CACR_DESB 0x20000000 /* Enable data store buffer */ 14 #define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */ 15 #define CACR_DHCLK 0x08000000 /* Half data cache lock mode */ 16 #define CACR_DDCM_WT 0x00000000 /* Write through cache*/ 17 #define CACR_DDCM_CP 0x02000000 /* Copyback cache */ 18 #define CACR_DDCM_P 0x04000000 /* No cache, precise */ 19 #define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ 20 #define CACR_DCINVA 0x01000000 /* Invalidate data cache */ 21 #define CACR_BEC 0x00080000 /* Enable branch cache */ 22 #define CACR_BCINVA 0x00040000 /* Invalidate branch cache */ 23 #define CACR_IEC 0x00008000 /* Enable instruction cache */ 24 #define CACR_DNFB 0x00002000 /* Inhibited fill buffer */ 25 #define CACR_IDPI 0x00001000 /* Disable CPUSHL */ 26 #define CACR_IHLCK 0x00000800 /* Intruction cache half lock */ 27 #define CACR_IDCM 0x00000400 /* Intruction cache inhibit */ 28 #define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ 29 30 #define ACR_BASE_POS 24 /* Address Base */ 31 #define ACR_MASK_POS 16 /* Address Mask */ 32 #define ACR_ENABLE 0x00008000 /* Enable address */ 33 #define ACR_USER 0x00000000 /* User mode access only */ 34 #define ACR_SUPER 0x00002000 /* Supervisor mode only */ 35 #define ACR_ANY 0x00004000 /* Match any access mode */ 36 #define ACR_CM_WT 0x00000000 /* Write through mode */ 37 #define ACR_CM_CP 0x00000020 /* Copyback mode */ 38 #define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ 39 #define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ 40 #define ACR_CM 0x00000060 /* Cache mode mask */ 41 #define ACR_WPROTECT 0x00000004 /* Write protect */ 42 43 #if defined(CONFIG_M5407) 44 45 #define ICACHE_SIZE 0x4000 /* instruction - 16k */ 46 #define DCACHE_SIZE 0x2000 /* data - 8k */ 47 48 #elif defined(CONFIG_M54xx) 49 50 #define ICACHE_SIZE 0x8000 /* instruction - 32k */ 51 #define DCACHE_SIZE 0x8000 /* data - 32k */ 52 53 #endif 54 55 #define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ 56 #define CACHE_WAYS 4 /* 4 ways */ 57 58 /* 59 * Version 4 cores have a true harvard style separate instruction 60 * and data cache. Enable data and instruction caches, also enable write 61 * buffers and branch accelerator. 62 */ 63 /* attention : enabling CACR_DESB requires a "nop" to flush the store buffer */ 64 /* use '+' instead of '|' for assembler's sake */ 65 66 /* Enable data cache */ 67 /* Enable data store buffer */ 68 /* outside ACRs : No cache, precise */ 69 /* Enable instruction+branch caches */ 70 #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC) 71 72 #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT) 73 74 #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) 75 76 #ifndef __ASSEMBLY__ 77 78 #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_WT) 79 #define flush_dcache_range(a, l) do { asm("nop"); } while (0) 80 #endif 81 82 static inline void __m54xx_flush_cache_all(void) 83 { 84 __asm__ __volatile__ ( 85 #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP) 86 /* 87 * Use cpushl to push and invalidate all cache lines. 88 * Gas doesn't seem to know how to generate the ColdFire 89 * cpushl instruction... Oh well, bit stuff it for now. 90 */ 91 "clrl %%d0\n\t" 92 "1:\n\t" 93 "movel %%d0,%%a0\n\t" 94 "2:\n\t" 95 ".word 0xf468\n\t" 96 "addl %0,%%a0\n\t" 97 "cmpl %1,%%a0\n\t" 98 "blt 2b\n\t" 99 "addql #1,%%d0\n\t" 100 "cmpil %2,%%d0\n\t" 101 "bne 1b\n\t" 102 #endif 103 "movel %3,%%d0\n\t" 104 "movec %%d0,%%CACR\n\t" 105 "nop\n\t" /* forces flush of Store Buffer */ 106 : /* No output */ 107 : "i" (CACHE_LINE_SIZE), 108 "i" (DCACHE_SIZE / CACHE_WAYS), 109 "i" (CACHE_WAYS), 110 "i" (CACHE_MODE|CACR_DCINVA|CACR_BCINVA|CACR_ICINVA) 111 : "d0", "a0" ); 112 } 113 114 #define __flush_cache_all() __m54xx_flush_cache_all() 115 116 #endif /* __ASSEMBLY__ */ 117 118 #endif /* m54xxacr_h */ 119