1bea8bcb1SSteven King /* 2bea8bcb1SSteven King * m5441xsim.h -- Coldfire 5441x register definitions 3bea8bcb1SSteven King * 4bea8bcb1SSteven King * (C) Copyright 2012, Steven King <sfking@fdwdc.com> 5bea8bcb1SSteven King */ 6bea8bcb1SSteven King 7bea8bcb1SSteven King #ifndef m5441xsim_h 8bea8bcb1SSteven King #define m5441xsim_h 9bea8bcb1SSteven King 10bea8bcb1SSteven King #define CPU_NAME "COLDFIRE(m5441x)" 11bea8bcb1SSteven King #define CPU_INSTR_PER_JIFFY 2 12bea8bcb1SSteven King #define MCF_BUSCLK (MCF_CLK / 2) 1381d33350SGreg Ungerer #define MACHINE MACH_M5441X 14cbd5b982SGreg Ungerer #define FPUTYPE 0 158cf4a973SGreg Ungerer #define IOMEMBASE 0xe0000000 168cf4a973SGreg Ungerer #define IOMEMSIZE 0x20000000 17bea8bcb1SSteven King 18bea8bcb1SSteven King #include <asm/m54xxacr.h> 19bea8bcb1SSteven King 20bea8bcb1SSteven King /* 21bea8bcb1SSteven King * Reset Controller Module. 22bea8bcb1SSteven King */ 23bea8bcb1SSteven King 24bea8bcb1SSteven King #define MCF_RCR 0xec090000 25bea8bcb1SSteven King #define MCF_RSR 0xec090001 26bea8bcb1SSteven King 27bea8bcb1SSteven King #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 28bea8bcb1SSteven King #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 29bea8bcb1SSteven King 30bea8bcb1SSteven King /* 31bea8bcb1SSteven King * Interrupt Controller Modules. 32bea8bcb1SSteven King */ 33bea8bcb1SSteven King /* the 5441x have 3 interrupt controllers, each control 64 interrupts */ 34bea8bcb1SSteven King #define MCFINT_VECBASE 64 35bea8bcb1SSteven King #define MCFINT0_VECBASE MCFINT_VECBASE 36bea8bcb1SSteven King #define MCFINT1_VECBASE (MCFINT0_VECBASE + 64) 37bea8bcb1SSteven King #define MCFINT2_VECBASE (MCFINT1_VECBASE + 64) 38bea8bcb1SSteven King 39bea8bcb1SSteven King /* interrupt controller 0 */ 40bea8bcb1SSteven King #define MCFINTC0_SIMR 0xfc04801c 41bea8bcb1SSteven King #define MCFINTC0_CIMR 0xfc04801d 42bea8bcb1SSteven King #define MCFINTC0_ICR0 0xfc048040 43bea8bcb1SSteven King /* interrupt controller 1 */ 44bea8bcb1SSteven King #define MCFINTC1_SIMR 0xfc04c01c 45bea8bcb1SSteven King #define MCFINTC1_CIMR 0xfc04c01d 46bea8bcb1SSteven King #define MCFINTC1_ICR0 0xfc04c040 47bea8bcb1SSteven King /* interrupt controller 2 */ 48bea8bcb1SSteven King #define MCFINTC2_SIMR 0xfc05001c 49bea8bcb1SSteven King #define MCFINTC2_CIMR 0xfc05001d 50bea8bcb1SSteven King #define MCFINTC2_ICR0 0xfc050040 51bea8bcb1SSteven King 52bea8bcb1SSteven King /* on interrupt controller 0 */ 53bea8bcb1SSteven King #define MCFINT0_EPORT0 1 54bea8bcb1SSteven King #define MCFINT0_UART0 26 55bea8bcb1SSteven King #define MCFINT0_UART1 27 56bea8bcb1SSteven King #define MCFINT0_UART2 28 57bea8bcb1SSteven King #define MCFINT0_UART3 29 58bea8bcb1SSteven King #define MCFINT0_I2C0 30 59bea8bcb1SSteven King #define MCFINT0_DSPI0 31 60bea8bcb1SSteven King 61bea8bcb1SSteven King #define MCFINT0_TIMER0 32 62bea8bcb1SSteven King #define MCFINT0_TIMER1 33 63bea8bcb1SSteven King #define MCFINT0_TIMER2 34 64bea8bcb1SSteven King #define MCFINT0_TIMER3 35 65bea8bcb1SSteven King 66bea8bcb1SSteven King #define MCFINT0_FECRX0 36 67bea8bcb1SSteven King #define MCFINT0_FECTX0 40 68bea8bcb1SSteven King #define MCFINT0_FECENTC0 42 69bea8bcb1SSteven King 70bea8bcb1SSteven King #define MCFINT0_FECRX1 49 71bea8bcb1SSteven King #define MCFINT0_FECTX1 53 72bea8bcb1SSteven King #define MCFINT0_FECENTC1 55 73bea8bcb1SSteven King 74bea8bcb1SSteven King /* on interrupt controller 1 */ 75bea8bcb1SSteven King #define MCFINT1_UART4 48 76bea8bcb1SSteven King #define MCFINT1_UART5 49 77bea8bcb1SSteven King #define MCFINT1_UART6 50 78bea8bcb1SSteven King #define MCFINT1_UART7 51 79bea8bcb1SSteven King #define MCFINT1_UART8 52 80bea8bcb1SSteven King #define MCFINT1_UART9 53 81bea8bcb1SSteven King #define MCFINT1_DSPI1 54 82bea8bcb1SSteven King #define MCFINT1_DSPI2 55 83bea8bcb1SSteven King #define MCFINT1_DSPI3 56 84bea8bcb1SSteven King #define MCFINT1_I2C1 57 85bea8bcb1SSteven King #define MCFINT1_I2C2 58 86bea8bcb1SSteven King #define MCFINT1_I2C3 59 87bea8bcb1SSteven King #define MCFINT1_I2C4 60 88bea8bcb1SSteven King #define MCFINT1_I2C5 61 89bea8bcb1SSteven King 90bea8bcb1SSteven King /* on interrupt controller 2 */ 91bea8bcb1SSteven King #define MCFINT2_PIT0 13 92bea8bcb1SSteven King #define MCFINT2_PIT1 14 93bea8bcb1SSteven King #define MCFINT2_PIT2 15 94bea8bcb1SSteven King #define MCFINT2_PIT3 16 95bea8bcb1SSteven King #define MCFINT2_RTC 26 96bea8bcb1SSteven King 97bea8bcb1SSteven King /* 98bea8bcb1SSteven King * PIT timer module. 99bea8bcb1SSteven King */ 100bea8bcb1SSteven King #define MCFPIT_BASE0 0xFC080000 /* Base address of TIMER0 */ 101bea8bcb1SSteven King #define MCFPIT_BASE1 0xFC084000 /* Base address of TIMER1 */ 102bea8bcb1SSteven King #define MCFPIT_BASE2 0xFC088000 /* Base address of TIMER2 */ 103bea8bcb1SSteven King #define MCFPIT_BASE3 0xFC08C000 /* Base address of TIMER3 */ 104bea8bcb1SSteven King 105bea8bcb1SSteven King 106bea8bcb1SSteven King #define MCF_IRQ_PIT1 (MCFINT2_VECBASE + MCFINT2_PIT1) 107bea8bcb1SSteven King 108bea8bcb1SSteven King /* 109bea8bcb1SSteven King * Power Management 110bea8bcb1SSteven King */ 111bea8bcb1SSteven King #define MCFPM_WCR 0xfc040013 112bea8bcb1SSteven King #define MCFPM_PPMSR0 0xfc04002c 113bea8bcb1SSteven King #define MCFPM_PPMCR0 0xfc04002d 114bea8bcb1SSteven King #define MCFPM_PPMSR1 0xfc04002e 115bea8bcb1SSteven King #define MCFPM_PPMCR1 0xfc04002f 116bea8bcb1SSteven King #define MCFPM_PPMHR0 0xfc040030 117bea8bcb1SSteven King #define MCFPM_PPMLR0 0xfc040034 118bea8bcb1SSteven King #define MCFPM_PPMHR1 0xfc040038 119bea8bcb1SSteven King #define MCFPM_PPMLR1 0xfc04003c 120bea8bcb1SSteven King #define MCFPM_LPCR 0xec090007 121bea8bcb1SSteven King /* 122bea8bcb1SSteven King * UART module. 123bea8bcb1SSteven King */ 124bea8bcb1SSteven King #define MCFUART_BASE0 0xfc060000 /* Base address of UART0 */ 125bea8bcb1SSteven King #define MCFUART_BASE1 0xfc064000 /* Base address of UART1 */ 126bea8bcb1SSteven King #define MCFUART_BASE2 0xfc068000 /* Base address of UART2 */ 127bea8bcb1SSteven King #define MCFUART_BASE3 0xfc06c000 /* Base address of UART3 */ 128bea8bcb1SSteven King #define MCFUART_BASE4 0xec060000 /* Base address of UART4 */ 129bea8bcb1SSteven King #define MCFUART_BASE5 0xec064000 /* Base address of UART5 */ 130bea8bcb1SSteven King #define MCFUART_BASE6 0xec068000 /* Base address of UART6 */ 131bea8bcb1SSteven King #define MCFUART_BASE7 0xec06c000 /* Base address of UART7 */ 132bea8bcb1SSteven King #define MCFUART_BASE8 0xec070000 /* Base address of UART8 */ 133bea8bcb1SSteven King #define MCFUART_BASE9 0xec074000 /* Base address of UART9 */ 134bea8bcb1SSteven King 135bea8bcb1SSteven King #define MCF_IRQ_UART0 (MCFINT0_VECBASE + MCFINT0_UART0) 136bea8bcb1SSteven King #define MCF_IRQ_UART1 (MCFINT0_VECBASE + MCFINT0_UART1) 137bea8bcb1SSteven King #define MCF_IRQ_UART2 (MCFINT0_VECBASE + MCFINT0_UART2) 138bea8bcb1SSteven King #define MCF_IRQ_UART3 (MCFINT0_VECBASE + MCFINT0_UART3) 139bea8bcb1SSteven King #define MCF_IRQ_UART4 (MCFINT1_VECBASE + MCFINT1_UART4) 140bea8bcb1SSteven King #define MCF_IRQ_UART5 (MCFINT1_VECBASE + MCFINT1_UART5) 141bea8bcb1SSteven King #define MCF_IRQ_UART6 (MCFINT1_VECBASE + MCFINT1_UART6) 142bea8bcb1SSteven King #define MCF_IRQ_UART7 (MCFINT1_VECBASE + MCFINT1_UART7) 143bea8bcb1SSteven King #define MCF_IRQ_UART8 (MCFINT1_VECBASE + MCFINT1_UART8) 144bea8bcb1SSteven King #define MCF_IRQ_UART9 (MCFINT1_VECBASE + MCFINT1_UART9) 145bea8bcb1SSteven King /* 146bea8bcb1SSteven King * FEC modules. 147bea8bcb1SSteven King */ 148bea8bcb1SSteven King #define MCFFEC_BASE0 0xfc0d4000 149bea8bcb1SSteven King #define MCFFEC_SIZE0 0x800 150bea8bcb1SSteven King #define MCF_IRQ_FECRX0 (MCFINT0_VECBASE + MCFINT0_FECRX0) 151bea8bcb1SSteven King #define MCF_IRQ_FECTX0 (MCFINT0_VECBASE + MCFINT0_FECTX0) 152bea8bcb1SSteven King #define MCF_IRQ_FECENTC0 (MCFINT0_VECBASE + MCFINT0_FECENTC0) 153bea8bcb1SSteven King 154bea8bcb1SSteven King #define MCFFEC_BASE1 0xfc0d8000 155bea8bcb1SSteven King #define MCFFEC_SIZE1 0x800 156bea8bcb1SSteven King #define MCF_IRQ_FECRX1 (MCFINT0_VECBASE + MCFINT0_FECRX1) 157bea8bcb1SSteven King #define MCF_IRQ_FECTX1 (MCFINT0_VECBASE + MCFINT0_FECTX1) 158bea8bcb1SSteven King #define MCF_IRQ_FECENTC1 (MCFINT0_VECBASE + MCFINT0_FECENTC1) 159bea8bcb1SSteven King /* 160bea8bcb1SSteven King * I2C modules. 161bea8bcb1SSteven King */ 162bea8bcb1SSteven King #define MCFI2C_BASE0 0xfc058000 163bea8bcb1SSteven King #define MCFI2C_SIZE0 0x20 164bea8bcb1SSteven King #define MCFI2C_BASE1 0xfc038000 165bea8bcb1SSteven King #define MCFI2C_SIZE1 0x20 166bea8bcb1SSteven King #define MCFI2C_BASE2 0xec010000 167bea8bcb1SSteven King #define MCFI2C_SIZE2 0x20 168bea8bcb1SSteven King #define MCFI2C_BASE3 0xec014000 169bea8bcb1SSteven King #define MCFI2C_SIZE3 0x20 170bea8bcb1SSteven King #define MCFI2C_BASE4 0xec018000 171bea8bcb1SSteven King #define MCFI2C_SIZE4 0x20 172bea8bcb1SSteven King #define MCFI2C_BASE5 0xec01c000 173bea8bcb1SSteven King #define MCFI2C_SIZE5 0x20 174bea8bcb1SSteven King 175bea8bcb1SSteven King #define MCF_IRQ_I2C0 (MCFINT0_VECBASE + MCFINT0_I2C0) 176bea8bcb1SSteven King #define MCF_IRQ_I2C1 (MCFINT1_VECBASE + MCFINT1_I2C1) 177bea8bcb1SSteven King #define MCF_IRQ_I2C2 (MCFINT1_VECBASE + MCFINT1_I2C2) 178bea8bcb1SSteven King #define MCF_IRQ_I2C3 (MCFINT1_VECBASE + MCFINT1_I2C3) 179bea8bcb1SSteven King #define MCF_IRQ_I2C4 (MCFINT1_VECBASE + MCFINT1_I2C4) 180bea8bcb1SSteven King #define MCF_IRQ_I2C5 (MCFINT1_VECBASE + MCFINT1_I2C5) 181bea8bcb1SSteven King /* 182bea8bcb1SSteven King * EPORT Module. 183bea8bcb1SSteven King */ 184bea8bcb1SSteven King #define MCFEPORT_EPPAR 0xfc090000 185bea8bcb1SSteven King #define MCFEPORT_EPIER 0xfc090003 186bea8bcb1SSteven King #define MCFEPORT_EPFR 0xfc090006 187c785a3d7SSteven King /* 188c785a3d7SSteven King * RTC Module. 189c785a3d7SSteven King */ 190c785a3d7SSteven King #define MCFRTC_BASE 0xfc0a8000 191c785a3d7SSteven King #define MCFRTC_SIZE (0xfc0a8840 - 0xfc0a8000) 192c785a3d7SSteven King #define MCF_IRQ_RTC (MCFINT2_VECBASE + MCFINT2_RTC) 193bea8bcb1SSteven King 194bea8bcb1SSteven King /* 195bea8bcb1SSteven King * GPIO Module. 196bea8bcb1SSteven King */ 197bea8bcb1SSteven King #define MCFGPIO_PODR_A 0xec094000 198bea8bcb1SSteven King #define MCFGPIO_PODR_B 0xec094001 199bea8bcb1SSteven King #define MCFGPIO_PODR_C 0xec094002 200bea8bcb1SSteven King #define MCFGPIO_PODR_D 0xec094003 201bea8bcb1SSteven King #define MCFGPIO_PODR_E 0xec094004 202bea8bcb1SSteven King #define MCFGPIO_PODR_F 0xec094005 203bea8bcb1SSteven King #define MCFGPIO_PODR_G 0xec094006 204bea8bcb1SSteven King #define MCFGPIO_PODR_H 0xec094007 205bea8bcb1SSteven King #define MCFGPIO_PODR_I 0xec094008 206bea8bcb1SSteven King #define MCFGPIO_PODR_J 0xec094009 207bea8bcb1SSteven King #define MCFGPIO_PODR_K 0xec09400a 208bea8bcb1SSteven King 209bea8bcb1SSteven King #define MCFGPIO_PDDR_A 0xec09400c 210bea8bcb1SSteven King #define MCFGPIO_PDDR_B 0xec09400d 211bea8bcb1SSteven King #define MCFGPIO_PDDR_C 0xec09400e 212bea8bcb1SSteven King #define MCFGPIO_PDDR_D 0xec09400f 213bea8bcb1SSteven King #define MCFGPIO_PDDR_E 0xec094010 214bea8bcb1SSteven King #define MCFGPIO_PDDR_F 0xec094011 215bea8bcb1SSteven King #define MCFGPIO_PDDR_G 0xec094012 216bea8bcb1SSteven King #define MCFGPIO_PDDR_H 0xec094013 217bea8bcb1SSteven King #define MCFGPIO_PDDR_I 0xec094014 218bea8bcb1SSteven King #define MCFGPIO_PDDR_J 0xec094015 219bea8bcb1SSteven King #define MCFGPIO_PDDR_K 0xec094016 220bea8bcb1SSteven King 221bea8bcb1SSteven King #define MCFGPIO_PPDSDR_A 0xec094018 222bea8bcb1SSteven King #define MCFGPIO_PPDSDR_B 0xec094019 223bea8bcb1SSteven King #define MCFGPIO_PPDSDR_C 0xec09401a 224bea8bcb1SSteven King #define MCFGPIO_PPDSDR_D 0xec09401b 225bea8bcb1SSteven King #define MCFGPIO_PPDSDR_E 0xec09401c 226bea8bcb1SSteven King #define MCFGPIO_PPDSDR_F 0xec09401d 227bea8bcb1SSteven King #define MCFGPIO_PPDSDR_G 0xec09401e 228bea8bcb1SSteven King #define MCFGPIO_PPDSDR_H 0xec09401f 229bea8bcb1SSteven King #define MCFGPIO_PPDSDR_I 0xec094020 230bea8bcb1SSteven King #define MCFGPIO_PPDSDR_J 0xec094021 231bea8bcb1SSteven King #define MCFGPIO_PPDSDR_K 0xec094022 232bea8bcb1SSteven King 233bea8bcb1SSteven King #define MCFGPIO_PCLRR_A 0xec094024 234bea8bcb1SSteven King #define MCFGPIO_PCLRR_B 0xec094025 235bea8bcb1SSteven King #define MCFGPIO_PCLRR_C 0xec094026 236bea8bcb1SSteven King #define MCFGPIO_PCLRR_D 0xec094027 237bea8bcb1SSteven King #define MCFGPIO_PCLRR_E 0xec094028 238bea8bcb1SSteven King #define MCFGPIO_PCLRR_F 0xec094029 239bea8bcb1SSteven King #define MCFGPIO_PCLRR_G 0xec09402a 240bea8bcb1SSteven King #define MCFGPIO_PCLRR_H 0xec09402b 241bea8bcb1SSteven King #define MCFGPIO_PCLRR_I 0xec09402c 242bea8bcb1SSteven King #define MCFGPIO_PCLRR_J 0xec09402d 243bea8bcb1SSteven King #define MCFGPIO_PCLRR_K 0xec09402e 244bea8bcb1SSteven King 245bea8bcb1SSteven King #define MCFGPIO_PAR_FBCTL 0xec094048 246bea8bcb1SSteven King #define MCFGPIO_PAR_BE 0xec094049 247bea8bcb1SSteven King #define MCFGPIO_PAR_CS 0xec09404a 248bea8bcb1SSteven King #define MCFGPIO_PAR_CANI2C 0xec09404b 249bea8bcb1SSteven King #define MCFGPIO_PAR_IRQ0H 0xec09404c 250bea8bcb1SSteven King #define MCFGPIO_PAR_IRQ0L 0xec09404d 251bea8bcb1SSteven King #define MCFGPIO_PAR_DSPIOWH 0xec09404e 252bea8bcb1SSteven King #define MCFGPIO_PAR_DSPIOWL 0xec09404f 253bea8bcb1SSteven King #define MCFGPIO_PAR_TIMER 0xec094050 254bea8bcb1SSteven King #define MCFGPIO_PAR_UART2 0xec094051 255bea8bcb1SSteven King #define MCFGPIO_PAR_UART1 0xec094052 256bea8bcb1SSteven King #define MCFGPIO_PAR_UART0 0xec094053 257bea8bcb1SSteven King #define MCFGPIO_PAR_SDHCH 0xec094054 258bea8bcb1SSteven King #define MCFGPIO_PAR_SDHCL 0xec094055 259bea8bcb1SSteven King #define MCFGPIO_PAR_SIMP0H 0xec094056 260bea8bcb1SSteven King #define MCFGPIO_PAR_SIMP0L 0xec094057 261bea8bcb1SSteven King #define MCFGPIO_PAR_SSI0H 0xec094058 262bea8bcb1SSteven King #define MCFGPIO_PAR_SSI0L 0xec094059 263bea8bcb1SSteven King #define MCFGPIO_PAR_DEBUGH1 0xec09405a 264bea8bcb1SSteven King #define MCFGPIO_PAR_DEBUGH0 0xec09405b 265bea8bcb1SSteven King #define MCFGPIO_PAR_DEBUGl 0xec09405c 266bea8bcb1SSteven King #define MCFGPIO_PAR_FEC 0xec09405e 267bea8bcb1SSteven King 268bea8bcb1SSteven King /* generalization for generic gpio support */ 269bea8bcb1SSteven King #define MCFGPIO_PODR MCFGPIO_PODR_A 270bea8bcb1SSteven King #define MCFGPIO_PDDR MCFGPIO_PDDR_A 271bea8bcb1SSteven King #define MCFGPIO_PPDR MCFGPIO_PPDSDR_A 272bea8bcb1SSteven King #define MCFGPIO_SETR MCFGPIO_PPDSDR_A 273bea8bcb1SSteven King #define MCFGPIO_CLRR MCFGPIO_PCLRR_A 274bea8bcb1SSteven King 275bea8bcb1SSteven King #define MCFGPIO_IRQ_MIN 17 276bea8bcb1SSteven King #define MCFGPIO_IRQ_MAX 24 277bea8bcb1SSteven King #define MCFGPIO_IRQ_VECBASE (MCFINT_VECBASE - MCFGPIO_IRQ_MIN) 278bea8bcb1SSteven King #define MCFGPIO_PIN_MAX 87 279bea8bcb1SSteven King 280bea8bcb1SSteven King #endif /* m5441xsim_h */ 281