1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2bea8bcb1SSteven King /* 3bea8bcb1SSteven King * m5441xsim.h -- Coldfire 5441x register definitions 4bea8bcb1SSteven King * 5bea8bcb1SSteven King * (C) Copyright 2012, Steven King <sfking@fdwdc.com> 6bea8bcb1SSteven King */ 7bea8bcb1SSteven King 8bea8bcb1SSteven King #ifndef m5441xsim_h 9bea8bcb1SSteven King #define m5441xsim_h 10bea8bcb1SSteven King 11bea8bcb1SSteven King #define CPU_NAME "COLDFIRE(m5441x)" 12bea8bcb1SSteven King #define CPU_INSTR_PER_JIFFY 2 13bea8bcb1SSteven King #define MCF_BUSCLK (MCF_CLK / 2) 1481d33350SGreg Ungerer #define MACHINE MACH_M5441X 15cbd5b982SGreg Ungerer #define FPUTYPE 0 168cf4a973SGreg Ungerer #define IOMEMBASE 0xe0000000 178cf4a973SGreg Ungerer #define IOMEMSIZE 0x20000000 18bea8bcb1SSteven King 19bea8bcb1SSteven King #include <asm/m54xxacr.h> 20bea8bcb1SSteven King 21bea8bcb1SSteven King /* 22bea8bcb1SSteven King * Reset Controller Module. 23bea8bcb1SSteven King */ 24bea8bcb1SSteven King 25bea8bcb1SSteven King #define MCF_RCR 0xec090000 26bea8bcb1SSteven King #define MCF_RSR 0xec090001 27bea8bcb1SSteven King 28bea8bcb1SSteven King #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 29bea8bcb1SSteven King #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 30bea8bcb1SSteven King 31bea8bcb1SSteven King /* 32bea8bcb1SSteven King * Interrupt Controller Modules. 33bea8bcb1SSteven King */ 34bea8bcb1SSteven King /* the 5441x have 3 interrupt controllers, each control 64 interrupts */ 35bea8bcb1SSteven King #define MCFINT_VECBASE 64 36bea8bcb1SSteven King #define MCFINT0_VECBASE MCFINT_VECBASE 37bea8bcb1SSteven King #define MCFINT1_VECBASE (MCFINT0_VECBASE + 64) 38bea8bcb1SSteven King #define MCFINT2_VECBASE (MCFINT1_VECBASE + 64) 39bea8bcb1SSteven King 40bea8bcb1SSteven King /* interrupt controller 0 */ 41bea8bcb1SSteven King #define MCFINTC0_SIMR 0xfc04801c 42bea8bcb1SSteven King #define MCFINTC0_CIMR 0xfc04801d 43bea8bcb1SSteven King #define MCFINTC0_ICR0 0xfc048040 44bea8bcb1SSteven King /* interrupt controller 1 */ 45bea8bcb1SSteven King #define MCFINTC1_SIMR 0xfc04c01c 46bea8bcb1SSteven King #define MCFINTC1_CIMR 0xfc04c01d 47bea8bcb1SSteven King #define MCFINTC1_ICR0 0xfc04c040 48bea8bcb1SSteven King /* interrupt controller 2 */ 49bea8bcb1SSteven King #define MCFINTC2_SIMR 0xfc05001c 50bea8bcb1SSteven King #define MCFINTC2_CIMR 0xfc05001d 51bea8bcb1SSteven King #define MCFINTC2_ICR0 0xfc050040 52bea8bcb1SSteven King 53bea8bcb1SSteven King /* on interrupt controller 0 */ 54bea8bcb1SSteven King #define MCFINT0_EPORT0 1 55bea8bcb1SSteven King #define MCFINT0_UART0 26 56bea8bcb1SSteven King #define MCFINT0_UART1 27 57bea8bcb1SSteven King #define MCFINT0_UART2 28 58bea8bcb1SSteven King #define MCFINT0_UART3 29 59bea8bcb1SSteven King #define MCFINT0_I2C0 30 60bea8bcb1SSteven King #define MCFINT0_DSPI0 31 61bea8bcb1SSteven King 62bea8bcb1SSteven King #define MCFINT0_TIMER0 32 63bea8bcb1SSteven King #define MCFINT0_TIMER1 33 64bea8bcb1SSteven King #define MCFINT0_TIMER2 34 65bea8bcb1SSteven King #define MCFINT0_TIMER3 35 66bea8bcb1SSteven King 67bea8bcb1SSteven King #define MCFINT0_FECRX0 36 68bea8bcb1SSteven King #define MCFINT0_FECTX0 40 69bea8bcb1SSteven King #define MCFINT0_FECENTC0 42 70bea8bcb1SSteven King 71bea8bcb1SSteven King #define MCFINT0_FECRX1 49 72bea8bcb1SSteven King #define MCFINT0_FECTX1 53 73bea8bcb1SSteven King #define MCFINT0_FECENTC1 55 74bea8bcb1SSteven King 75bea8bcb1SSteven King /* on interrupt controller 1 */ 76*35a9f936SAngelo Dureghello #define MCFINT1_FLEXCAN0_IFL 0 77*35a9f936SAngelo Dureghello #define MCFINT1_FLEXCAN0_BOFF 1 78*35a9f936SAngelo Dureghello #define MCFINT1_FLEXCAN0_ERR 3 79*35a9f936SAngelo Dureghello #define MCFINT1_FLEXCAN1_IFL 4 80*35a9f936SAngelo Dureghello #define MCFINT1_FLEXCAN1_BOFF 5 81*35a9f936SAngelo Dureghello #define MCFINT1_FLEXCAN1_ERR 7 82bea8bcb1SSteven King #define MCFINT1_UART4 48 83bea8bcb1SSteven King #define MCFINT1_UART5 49 84bea8bcb1SSteven King #define MCFINT1_UART6 50 85bea8bcb1SSteven King #define MCFINT1_UART7 51 86bea8bcb1SSteven King #define MCFINT1_UART8 52 87bea8bcb1SSteven King #define MCFINT1_UART9 53 88bea8bcb1SSteven King #define MCFINT1_DSPI1 54 89bea8bcb1SSteven King #define MCFINT1_DSPI2 55 90bea8bcb1SSteven King #define MCFINT1_DSPI3 56 91bea8bcb1SSteven King #define MCFINT1_I2C1 57 92bea8bcb1SSteven King #define MCFINT1_I2C2 58 93bea8bcb1SSteven King #define MCFINT1_I2C3 59 94bea8bcb1SSteven King #define MCFINT1_I2C4 60 95bea8bcb1SSteven King #define MCFINT1_I2C5 61 96bea8bcb1SSteven King 97bea8bcb1SSteven King /* on interrupt controller 2 */ 98bea8bcb1SSteven King #define MCFINT2_PIT0 13 99bea8bcb1SSteven King #define MCFINT2_PIT1 14 100bea8bcb1SSteven King #define MCFINT2_PIT2 15 101bea8bcb1SSteven King #define MCFINT2_PIT3 16 102bea8bcb1SSteven King #define MCFINT2_RTC 26 103bea8bcb1SSteven King 104bea8bcb1SSteven King /* 105bea8bcb1SSteven King * PIT timer module. 106bea8bcb1SSteven King */ 107bea8bcb1SSteven King #define MCFPIT_BASE0 0xFC080000 /* Base address of TIMER0 */ 108bea8bcb1SSteven King #define MCFPIT_BASE1 0xFC084000 /* Base address of TIMER1 */ 109bea8bcb1SSteven King #define MCFPIT_BASE2 0xFC088000 /* Base address of TIMER2 */ 110bea8bcb1SSteven King #define MCFPIT_BASE3 0xFC08C000 /* Base address of TIMER3 */ 111bea8bcb1SSteven King 112bea8bcb1SSteven King 113bea8bcb1SSteven King #define MCF_IRQ_PIT1 (MCFINT2_VECBASE + MCFINT2_PIT1) 114bea8bcb1SSteven King 115bea8bcb1SSteven King /* 116bea8bcb1SSteven King * Power Management 117bea8bcb1SSteven King */ 118bea8bcb1SSteven King #define MCFPM_WCR 0xfc040013 119bea8bcb1SSteven King #define MCFPM_PPMSR0 0xfc04002c 120bea8bcb1SSteven King #define MCFPM_PPMCR0 0xfc04002d 121bea8bcb1SSteven King #define MCFPM_PPMSR1 0xfc04002e 122bea8bcb1SSteven King #define MCFPM_PPMCR1 0xfc04002f 123bea8bcb1SSteven King #define MCFPM_PPMHR0 0xfc040030 124bea8bcb1SSteven King #define MCFPM_PPMLR0 0xfc040034 125bea8bcb1SSteven King #define MCFPM_PPMHR1 0xfc040038 126bea8bcb1SSteven King #define MCFPM_PPMLR1 0xfc04003c 127bea8bcb1SSteven King #define MCFPM_LPCR 0xec090007 128bea8bcb1SSteven King /* 129bea8bcb1SSteven King * UART module. 130bea8bcb1SSteven King */ 131bea8bcb1SSteven King #define MCFUART_BASE0 0xfc060000 /* Base address of UART0 */ 132bea8bcb1SSteven King #define MCFUART_BASE1 0xfc064000 /* Base address of UART1 */ 133bea8bcb1SSteven King #define MCFUART_BASE2 0xfc068000 /* Base address of UART2 */ 134bea8bcb1SSteven King #define MCFUART_BASE3 0xfc06c000 /* Base address of UART3 */ 135bea8bcb1SSteven King #define MCFUART_BASE4 0xec060000 /* Base address of UART4 */ 136bea8bcb1SSteven King #define MCFUART_BASE5 0xec064000 /* Base address of UART5 */ 137bea8bcb1SSteven King #define MCFUART_BASE6 0xec068000 /* Base address of UART6 */ 138bea8bcb1SSteven King #define MCFUART_BASE7 0xec06c000 /* Base address of UART7 */ 139bea8bcb1SSteven King #define MCFUART_BASE8 0xec070000 /* Base address of UART8 */ 140bea8bcb1SSteven King #define MCFUART_BASE9 0xec074000 /* Base address of UART9 */ 141bea8bcb1SSteven King 142bea8bcb1SSteven King #define MCF_IRQ_UART0 (MCFINT0_VECBASE + MCFINT0_UART0) 143bea8bcb1SSteven King #define MCF_IRQ_UART1 (MCFINT0_VECBASE + MCFINT0_UART1) 144bea8bcb1SSteven King #define MCF_IRQ_UART2 (MCFINT0_VECBASE + MCFINT0_UART2) 145bea8bcb1SSteven King #define MCF_IRQ_UART3 (MCFINT0_VECBASE + MCFINT0_UART3) 146bea8bcb1SSteven King #define MCF_IRQ_UART4 (MCFINT1_VECBASE + MCFINT1_UART4) 147bea8bcb1SSteven King #define MCF_IRQ_UART5 (MCFINT1_VECBASE + MCFINT1_UART5) 148bea8bcb1SSteven King #define MCF_IRQ_UART6 (MCFINT1_VECBASE + MCFINT1_UART6) 149bea8bcb1SSteven King #define MCF_IRQ_UART7 (MCFINT1_VECBASE + MCFINT1_UART7) 150bea8bcb1SSteven King #define MCF_IRQ_UART8 (MCFINT1_VECBASE + MCFINT1_UART8) 151bea8bcb1SSteven King #define MCF_IRQ_UART9 (MCFINT1_VECBASE + MCFINT1_UART9) 152bea8bcb1SSteven King /* 153bea8bcb1SSteven King * FEC modules. 154bea8bcb1SSteven King */ 155bea8bcb1SSteven King #define MCFFEC_BASE0 0xfc0d4000 156bea8bcb1SSteven King #define MCFFEC_SIZE0 0x800 157bea8bcb1SSteven King #define MCF_IRQ_FECRX0 (MCFINT0_VECBASE + MCFINT0_FECRX0) 158bea8bcb1SSteven King #define MCF_IRQ_FECTX0 (MCFINT0_VECBASE + MCFINT0_FECTX0) 159bea8bcb1SSteven King #define MCF_IRQ_FECENTC0 (MCFINT0_VECBASE + MCFINT0_FECENTC0) 160bea8bcb1SSteven King 161bea8bcb1SSteven King #define MCFFEC_BASE1 0xfc0d8000 162bea8bcb1SSteven King #define MCFFEC_SIZE1 0x800 163bea8bcb1SSteven King #define MCF_IRQ_FECRX1 (MCFINT0_VECBASE + MCFINT0_FECRX1) 164bea8bcb1SSteven King #define MCF_IRQ_FECTX1 (MCFINT0_VECBASE + MCFINT0_FECTX1) 165bea8bcb1SSteven King #define MCF_IRQ_FECENTC1 (MCFINT0_VECBASE + MCFINT0_FECENTC1) 166bea8bcb1SSteven King /* 167bea8bcb1SSteven King * I2C modules. 168bea8bcb1SSteven King */ 169bea8bcb1SSteven King #define MCFI2C_BASE0 0xfc058000 170bea8bcb1SSteven King #define MCFI2C_SIZE0 0x20 171bea8bcb1SSteven King #define MCFI2C_BASE1 0xfc038000 172bea8bcb1SSteven King #define MCFI2C_SIZE1 0x20 173bea8bcb1SSteven King #define MCFI2C_BASE2 0xec010000 174bea8bcb1SSteven King #define MCFI2C_SIZE2 0x20 175bea8bcb1SSteven King #define MCFI2C_BASE3 0xec014000 176bea8bcb1SSteven King #define MCFI2C_SIZE3 0x20 177bea8bcb1SSteven King #define MCFI2C_BASE4 0xec018000 178bea8bcb1SSteven King #define MCFI2C_SIZE4 0x20 179bea8bcb1SSteven King #define MCFI2C_BASE5 0xec01c000 180bea8bcb1SSteven King #define MCFI2C_SIZE5 0x20 181bea8bcb1SSteven King 182bea8bcb1SSteven King #define MCF_IRQ_I2C0 (MCFINT0_VECBASE + MCFINT0_I2C0) 183bea8bcb1SSteven King #define MCF_IRQ_I2C1 (MCFINT1_VECBASE + MCFINT1_I2C1) 184bea8bcb1SSteven King #define MCF_IRQ_I2C2 (MCFINT1_VECBASE + MCFINT1_I2C2) 185bea8bcb1SSteven King #define MCF_IRQ_I2C3 (MCFINT1_VECBASE + MCFINT1_I2C3) 186bea8bcb1SSteven King #define MCF_IRQ_I2C4 (MCFINT1_VECBASE + MCFINT1_I2C4) 187bea8bcb1SSteven King #define MCF_IRQ_I2C5 (MCFINT1_VECBASE + MCFINT1_I2C5) 188bea8bcb1SSteven King /* 189bea8bcb1SSteven King * EPORT Module. 190bea8bcb1SSteven King */ 191bea8bcb1SSteven King #define MCFEPORT_EPPAR 0xfc090000 192bea8bcb1SSteven King #define MCFEPORT_EPIER 0xfc090003 193bea8bcb1SSteven King #define MCFEPORT_EPFR 0xfc090006 194c785a3d7SSteven King /* 195c785a3d7SSteven King * RTC Module. 196c785a3d7SSteven King */ 197c785a3d7SSteven King #define MCFRTC_BASE 0xfc0a8000 198c785a3d7SSteven King #define MCFRTC_SIZE (0xfc0a8840 - 0xfc0a8000) 199c785a3d7SSteven King #define MCF_IRQ_RTC (MCFINT2_VECBASE + MCFINT2_RTC) 200bea8bcb1SSteven King 201bea8bcb1SSteven King /* 202bea8bcb1SSteven King * GPIO Module. 203bea8bcb1SSteven King */ 204bea8bcb1SSteven King #define MCFGPIO_PODR_A 0xec094000 205bea8bcb1SSteven King #define MCFGPIO_PODR_B 0xec094001 206bea8bcb1SSteven King #define MCFGPIO_PODR_C 0xec094002 207bea8bcb1SSteven King #define MCFGPIO_PODR_D 0xec094003 208bea8bcb1SSteven King #define MCFGPIO_PODR_E 0xec094004 209bea8bcb1SSteven King #define MCFGPIO_PODR_F 0xec094005 210bea8bcb1SSteven King #define MCFGPIO_PODR_G 0xec094006 211bea8bcb1SSteven King #define MCFGPIO_PODR_H 0xec094007 212bea8bcb1SSteven King #define MCFGPIO_PODR_I 0xec094008 213bea8bcb1SSteven King #define MCFGPIO_PODR_J 0xec094009 214bea8bcb1SSteven King #define MCFGPIO_PODR_K 0xec09400a 215bea8bcb1SSteven King 216bea8bcb1SSteven King #define MCFGPIO_PDDR_A 0xec09400c 217bea8bcb1SSteven King #define MCFGPIO_PDDR_B 0xec09400d 218bea8bcb1SSteven King #define MCFGPIO_PDDR_C 0xec09400e 219bea8bcb1SSteven King #define MCFGPIO_PDDR_D 0xec09400f 220bea8bcb1SSteven King #define MCFGPIO_PDDR_E 0xec094010 221bea8bcb1SSteven King #define MCFGPIO_PDDR_F 0xec094011 222bea8bcb1SSteven King #define MCFGPIO_PDDR_G 0xec094012 223bea8bcb1SSteven King #define MCFGPIO_PDDR_H 0xec094013 224bea8bcb1SSteven King #define MCFGPIO_PDDR_I 0xec094014 225bea8bcb1SSteven King #define MCFGPIO_PDDR_J 0xec094015 226bea8bcb1SSteven King #define MCFGPIO_PDDR_K 0xec094016 227bea8bcb1SSteven King 228bea8bcb1SSteven King #define MCFGPIO_PPDSDR_A 0xec094018 229bea8bcb1SSteven King #define MCFGPIO_PPDSDR_B 0xec094019 230bea8bcb1SSteven King #define MCFGPIO_PPDSDR_C 0xec09401a 231bea8bcb1SSteven King #define MCFGPIO_PPDSDR_D 0xec09401b 232bea8bcb1SSteven King #define MCFGPIO_PPDSDR_E 0xec09401c 233bea8bcb1SSteven King #define MCFGPIO_PPDSDR_F 0xec09401d 234bea8bcb1SSteven King #define MCFGPIO_PPDSDR_G 0xec09401e 235bea8bcb1SSteven King #define MCFGPIO_PPDSDR_H 0xec09401f 236bea8bcb1SSteven King #define MCFGPIO_PPDSDR_I 0xec094020 237bea8bcb1SSteven King #define MCFGPIO_PPDSDR_J 0xec094021 238bea8bcb1SSteven King #define MCFGPIO_PPDSDR_K 0xec094022 239bea8bcb1SSteven King 240bea8bcb1SSteven King #define MCFGPIO_PCLRR_A 0xec094024 241bea8bcb1SSteven King #define MCFGPIO_PCLRR_B 0xec094025 242bea8bcb1SSteven King #define MCFGPIO_PCLRR_C 0xec094026 243bea8bcb1SSteven King #define MCFGPIO_PCLRR_D 0xec094027 244bea8bcb1SSteven King #define MCFGPIO_PCLRR_E 0xec094028 245bea8bcb1SSteven King #define MCFGPIO_PCLRR_F 0xec094029 246bea8bcb1SSteven King #define MCFGPIO_PCLRR_G 0xec09402a 247bea8bcb1SSteven King #define MCFGPIO_PCLRR_H 0xec09402b 248bea8bcb1SSteven King #define MCFGPIO_PCLRR_I 0xec09402c 249bea8bcb1SSteven King #define MCFGPIO_PCLRR_J 0xec09402d 250bea8bcb1SSteven King #define MCFGPIO_PCLRR_K 0xec09402e 251bea8bcb1SSteven King 252bea8bcb1SSteven King #define MCFGPIO_PAR_FBCTL 0xec094048 253bea8bcb1SSteven King #define MCFGPIO_PAR_BE 0xec094049 254bea8bcb1SSteven King #define MCFGPIO_PAR_CS 0xec09404a 255bea8bcb1SSteven King #define MCFGPIO_PAR_CANI2C 0xec09404b 256bea8bcb1SSteven King #define MCFGPIO_PAR_IRQ0H 0xec09404c 257bea8bcb1SSteven King #define MCFGPIO_PAR_IRQ0L 0xec09404d 258bea8bcb1SSteven King #define MCFGPIO_PAR_DSPIOWH 0xec09404e 259bea8bcb1SSteven King #define MCFGPIO_PAR_DSPIOWL 0xec09404f 260bea8bcb1SSteven King #define MCFGPIO_PAR_TIMER 0xec094050 261bea8bcb1SSteven King #define MCFGPIO_PAR_UART2 0xec094051 262bea8bcb1SSteven King #define MCFGPIO_PAR_UART1 0xec094052 263bea8bcb1SSteven King #define MCFGPIO_PAR_UART0 0xec094053 264bea8bcb1SSteven King #define MCFGPIO_PAR_SDHCH 0xec094054 265bea8bcb1SSteven King #define MCFGPIO_PAR_SDHCL 0xec094055 266bea8bcb1SSteven King #define MCFGPIO_PAR_SIMP0H 0xec094056 267bea8bcb1SSteven King #define MCFGPIO_PAR_SIMP0L 0xec094057 268bea8bcb1SSteven King #define MCFGPIO_PAR_SSI0H 0xec094058 269bea8bcb1SSteven King #define MCFGPIO_PAR_SSI0L 0xec094059 270bea8bcb1SSteven King #define MCFGPIO_PAR_DEBUGH1 0xec09405a 271bea8bcb1SSteven King #define MCFGPIO_PAR_DEBUGH0 0xec09405b 272bea8bcb1SSteven King #define MCFGPIO_PAR_DEBUGl 0xec09405c 273bea8bcb1SSteven King #define MCFGPIO_PAR_FEC 0xec09405e 274bea8bcb1SSteven King 275bea8bcb1SSteven King /* generalization for generic gpio support */ 276bea8bcb1SSteven King #define MCFGPIO_PODR MCFGPIO_PODR_A 277bea8bcb1SSteven King #define MCFGPIO_PDDR MCFGPIO_PDDR_A 278bea8bcb1SSteven King #define MCFGPIO_PPDR MCFGPIO_PPDSDR_A 279bea8bcb1SSteven King #define MCFGPIO_SETR MCFGPIO_PPDSDR_A 280bea8bcb1SSteven King #define MCFGPIO_CLRR MCFGPIO_PCLRR_A 281bea8bcb1SSteven King 282bea8bcb1SSteven King #define MCFGPIO_IRQ_MIN 17 283bea8bcb1SSteven King #define MCFGPIO_IRQ_MAX 24 284bea8bcb1SSteven King #define MCFGPIO_IRQ_VECBASE (MCFINT_VECBASE - MCFGPIO_IRQ_MIN) 285bea8bcb1SSteven King #define MCFGPIO_PIN_MAX 87 286bea8bcb1SSteven King 28708fe92e2SAngelo Dureghello /* 288991f5c4dSAngelo Dureghello * Phase Locked Loop (PLL) 289991f5c4dSAngelo Dureghello */ 290991f5c4dSAngelo Dureghello #define MCF_PLL_CR 0xFC0C0000 291991f5c4dSAngelo Dureghello #define MCF_PLL_DR 0xFC0C0004 292991f5c4dSAngelo Dureghello #define MCF_PLL_SR 0xFC0C0008 293991f5c4dSAngelo Dureghello 294991f5c4dSAngelo Dureghello /* 29508fe92e2SAngelo Dureghello * DSPI module. 29608fe92e2SAngelo Dureghello */ 29708fe92e2SAngelo Dureghello #define MCFDSPI_BASE0 0xfc05c000 298d7e9d01aSAngelo Dureghello #define MCFDSPI_BASE1 0xfC03c000 29908fe92e2SAngelo Dureghello #define MCF_IRQ_DSPI0 (MCFINT0_VECBASE + MCFINT0_DSPI0) 300d7e9d01aSAngelo Dureghello #define MCF_IRQ_DSPI1 (MCFINT1_VECBASE + MCFINT1_DSPI1) 301d7e9d01aSAngelo Dureghello /* 302d7e9d01aSAngelo Dureghello * eDMA module. 303d7e9d01aSAngelo Dureghello */ 304d7e9d01aSAngelo Dureghello #define MCFEDMA_BASE 0xfc044000 305d7e9d01aSAngelo Dureghello #define MCFEDMA_SIZE 0x4000 306d7e9d01aSAngelo Dureghello #define MCFINT0_EDMA_INTR0 8 307d7e9d01aSAngelo Dureghello #define MCFINT0_EDMA_ERR 24 308d7e9d01aSAngelo Dureghello #define MCFEDMA_EDMA_INTR16 8 309d7e9d01aSAngelo Dureghello #define MCFEDMA_EDMA_INTR56 0 310d7e9d01aSAngelo Dureghello #define MCFEDMA_IRQ_INTR0 (MCFINT0_VECBASE + MCFINT0_EDMA_INTR0) 311d7e9d01aSAngelo Dureghello #define MCFEDMA_IRQ_INTR16 (MCFINT1_VECBASE + MCFEDMA_EDMA_INTR16) 312d7e9d01aSAngelo Dureghello #define MCFEDMA_IRQ_INTR56 (MCFINT2_VECBASE + MCFEDMA_EDMA_INTR56) 313d7e9d01aSAngelo Dureghello #define MCFEDMA_IRQ_ERR (MCFINT0_VECBASE + MCFINT0_EDMA_ERR) 314991f5c4dSAngelo Dureghello /* 315991f5c4dSAngelo Dureghello * esdhc module. 316991f5c4dSAngelo Dureghello */ 317991f5c4dSAngelo Dureghello #define MCFSDHC_BASE 0xfc0cc000 318991f5c4dSAngelo Dureghello #define MCFSDHC_SIZE 256 319991f5c4dSAngelo Dureghello #define MCFINT2_SDHC 31 320991f5c4dSAngelo Dureghello #define MCF_IRQ_SDHC (MCFINT2_VECBASE + MCFINT2_SDHC) 321991f5c4dSAngelo Dureghello #define MCFSDHC_CLK (MCFSDHC_BASE + 0x2c) 32208fe92e2SAngelo Dureghello 323*35a9f936SAngelo Dureghello /* 324*35a9f936SAngelo Dureghello * Flexcan module 325*35a9f936SAngelo Dureghello */ 326*35a9f936SAngelo Dureghello #define MCFFLEXCAN_BASE0 0xfc020000 327*35a9f936SAngelo Dureghello #define MCFFLEXCAN_BASE1 0xfc024000 328*35a9f936SAngelo Dureghello #define MCFFLEXCAN_SIZE 0x4000 329*35a9f936SAngelo Dureghello #define MCF_IRQ_IFL0 (MCFINT1_VECBASE + MCFINT1_FLEXCAN0_IFL) 330*35a9f936SAngelo Dureghello #define MCF_IRQ_BOFF0 (MCFINT1_VECBASE + MCFINT1_FLEXCAN0_BOFF) 331*35a9f936SAngelo Dureghello #define MCF_IRQ_ERR0 (MCFINT1_VECBASE + MCFINT1_FLEXCAN0_ERR) 332*35a9f936SAngelo Dureghello #define MCF_IRQ_IFL1 (MCFINT1_VECBASE + MCFINT1_FLEXCAN1_IFL) 333*35a9f936SAngelo Dureghello #define MCF_IRQ_BOFF1 (MCFINT1_VECBASE + MCFINT1_FLEXCAN1_BOFF) 334*35a9f936SAngelo Dureghello #define MCF_IRQ_ERR1 (MCFINT1_VECBASE + MCFINT1_FLEXCAN1_ERR) 335*35a9f936SAngelo Dureghello 336bea8bcb1SSteven King #endif /* m5441xsim_h */ 337