149148020SSam Ravnborg /****************************************************************************/ 249148020SSam Ravnborg 349148020SSam Ravnborg /* 449148020SSam Ravnborg * m5407sim.h -- ColdFire 5407 System Integration Module support. 549148020SSam Ravnborg * 649148020SSam Ravnborg * (C) Copyright 2000, Lineo (www.lineo.com) 749148020SSam Ravnborg * (C) Copyright 1999, Moreton Bay Ventures Pty Ltd. 849148020SSam Ravnborg * 949148020SSam Ravnborg * Modified by David W. Miller for the MCF5307 Eval Board. 1049148020SSam Ravnborg */ 1149148020SSam Ravnborg 1249148020SSam Ravnborg /****************************************************************************/ 1349148020SSam Ravnborg #ifndef m5407sim_h 1449148020SSam Ravnborg #define m5407sim_h 1549148020SSam Ravnborg /****************************************************************************/ 1649148020SSam Ravnborg 177fc82b65SGreg Ungerer #define CPU_NAME "COLDFIRE(m5407)" 18733f31b7SGreg Ungerer #define CPU_INSTR_PER_JIFFY 3 19ce3de78aSGreg Ungerer #define MCF_BUSCLK (MCF_CLK / 2) 207fc82b65SGreg Ungerer 213d461401SGreg Ungerer #include <asm/m54xxacr.h> 223d461401SGreg Ungerer 2349148020SSam Ravnborg /* 2449148020SSam Ravnborg * Define the 5407 SIM register set addresses. 2549148020SSam Ravnborg */ 26e1e362dcSGreg Ungerer #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */ 27e1e362dcSGreg Ungerer #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ 28660b73e3SGreg Ungerer #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ 29660b73e3SGreg Ungerer #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/ 30a45f56b2SGreg Ungerer #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */ 3135142b91SGreg Ungerer #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */ 3235142b91SGreg Ungerer #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl */ 3335142b91SGreg Ungerer #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */ 346a3a786dSGreg Ungerer #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */ 356a3a786dSGreg Ungerer #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */ 366a3a786dSGreg Ungerer #define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */ 37c986a3d5SGreg Ungerer #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */ 38c986a3d5SGreg Ungerer #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */ 39c986a3d5SGreg Ungerer #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */ 40c986a3d5SGreg Ungerer #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */ 41c986a3d5SGreg Ungerer #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */ 42c986a3d5SGreg Ungerer #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */ 43c986a3d5SGreg Ungerer #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */ 44c986a3d5SGreg Ungerer #define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */ 45c986a3d5SGreg Ungerer #define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */ 46c986a3d5SGreg Ungerer #define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */ 47c986a3d5SGreg Ungerer #define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */ 48c986a3d5SGreg Ungerer #define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */ 4949148020SSam Ravnborg 501419ea3bSGreg Ungerer #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */ 511419ea3bSGreg Ungerer #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */ 521419ea3bSGreg Ungerer #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */ 531419ea3bSGreg Ungerer #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */ 541419ea3bSGreg Ungerer #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */ 551419ea3bSGreg Ungerer #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */ 5649148020SSam Ravnborg 571419ea3bSGreg Ungerer #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */ 581419ea3bSGreg Ungerer #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */ 591419ea3bSGreg Ungerer #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ 601419ea3bSGreg Ungerer #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */ 611419ea3bSGreg Ungerer #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */ 621419ea3bSGreg Ungerer #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ 631419ea3bSGreg Ungerer #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */ 641419ea3bSGreg Ungerer #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */ 651419ea3bSGreg Ungerer #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */ 661419ea3bSGreg Ungerer #define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */ 671419ea3bSGreg Ungerer #define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */ 681419ea3bSGreg Ungerer #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */ 691419ea3bSGreg Ungerer #define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */ 701419ea3bSGreg Ungerer #define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */ 711419ea3bSGreg Ungerer #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */ 721419ea3bSGreg Ungerer #define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */ 731419ea3bSGreg Ungerer #define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */ 741419ea3bSGreg Ungerer #define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */ 7549148020SSam Ravnborg 766a92e198SGreg Ungerer #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ 776a92e198SGreg Ungerer #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ 786a92e198SGreg Ungerer #define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */ 796a92e198SGreg Ungerer #define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */ 806a92e198SGreg Ungerer #define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */ 8149148020SSam Ravnborg 8258f0ac98SGreg Ungerer /* 8358f0ac98SGreg Ungerer * Timer module. 8458f0ac98SGreg Ungerer */ 8558f0ac98SGreg Ungerer #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ 8658f0ac98SGreg Ungerer #define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ 8758f0ac98SGreg Ungerer 8869d23b61SGreg Ungerer #define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */ 8969d23b61SGreg Ungerer #define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */ 9057015421SGreg Ungerer 91dca7cf33Ssfking@fdwdc.com #define MCFSIM_PADDR (MCF_MBAR + 0x244) 92dca7cf33Ssfking@fdwdc.com #define MCFSIM_PADAT (MCF_MBAR + 0x248) 9349148020SSam Ravnborg 94dca7cf33Ssfking@fdwdc.com /* 95babc08b7SGreg Ungerer * DMA unit base addresses. 96babc08b7SGreg Ungerer */ 97babc08b7SGreg Ungerer #define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ 98babc08b7SGreg Ungerer #define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ 99babc08b7SGreg Ungerer #define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ 100babc08b7SGreg Ungerer #define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ 101babc08b7SGreg Ungerer 102babc08b7SGreg Ungerer /* 103dca7cf33Ssfking@fdwdc.com * Generic GPIO support 104dca7cf33Ssfking@fdwdc.com */ 105dca7cf33Ssfking@fdwdc.com #define MCFGPIO_PIN_MAX 16 106dca7cf33Ssfking@fdwdc.com #define MCFGPIO_IRQ_MAX -1 107dca7cf33Ssfking@fdwdc.com #define MCFGPIO_IRQ_VECBASE -1 10849148020SSam Ravnborg 10949148020SSam Ravnborg /* 11049148020SSam Ravnborg * Some symbol defines for the above... 11149148020SSam Ravnborg */ 11249148020SSam Ravnborg #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ 11349148020SSam Ravnborg #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ 11449148020SSam Ravnborg #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ 11549148020SSam Ravnborg #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ 11649148020SSam Ravnborg #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ 11749148020SSam Ravnborg #define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ 11849148020SSam Ravnborg #define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ 11949148020SSam Ravnborg #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ 12049148020SSam Ravnborg #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 12149148020SSam Ravnborg 12249148020SSam Ravnborg /* 12349148020SSam Ravnborg * Some symbol defines for the Parallel Port Pin Assignment Register 12449148020SSam Ravnborg */ 12549148020SSam Ravnborg #define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */ 12649148020SSam Ravnborg /* Clear to select par I/O */ 12749148020SSam Ravnborg #define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */ 12849148020SSam Ravnborg /* Clear to select par I/O */ 12949148020SSam Ravnborg 13049148020SSam Ravnborg /* 13149148020SSam Ravnborg * Defines for the IRQPAR Register 13249148020SSam Ravnborg */ 13349148020SSam Ravnborg #define IRQ5_LEVEL4 0x80 13449148020SSam Ravnborg #define IRQ3_LEVEL6 0x40 13549148020SSam Ravnborg #define IRQ1_LEVEL2 0x20 13649148020SSam Ravnborg 13704b75b10SGreg Ungerer /* 13804b75b10SGreg Ungerer * Define system peripheral IRQ usage. 13904b75b10SGreg Ungerer */ 14004b75b10SGreg Ungerer #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 14104b75b10SGreg Ungerer #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 14269d23b61SGreg Ungerer #define MCF_IRQ_UART0 73 /* UART0 */ 14369d23b61SGreg Ungerer #define MCF_IRQ_UART1 74 /* UART1 */ 14449148020SSam Ravnborg 14549148020SSam Ravnborg /****************************************************************************/ 14649148020SSam Ravnborg #endif /* m5407sim_h */ 147