16eac4027SGreg Ungerer /****************************************************************************/ 26eac4027SGreg Ungerer 36eac4027SGreg Ungerer /* 46eac4027SGreg Ungerer * m53xxsim.h -- ColdFire 5329 registers 56eac4027SGreg Ungerer */ 66eac4027SGreg Ungerer 76eac4027SGreg Ungerer /****************************************************************************/ 86eac4027SGreg Ungerer #ifndef m53xxsim_h 96eac4027SGreg Ungerer #define m53xxsim_h 106eac4027SGreg Ungerer /****************************************************************************/ 116eac4027SGreg Ungerer 126eac4027SGreg Ungerer #define CPU_NAME "COLDFIRE(m53xx)" 136eac4027SGreg Ungerer #define CPU_INSTR_PER_JIFFY 3 146eac4027SGreg Ungerer #define MCF_BUSCLK (MCF_CLK / 3) 156eac4027SGreg Ungerer 166eac4027SGreg Ungerer #include <asm/m53xxacr.h> 176eac4027SGreg Ungerer 186eac4027SGreg Ungerer #define MCFINT_VECBASE 64 196eac4027SGreg Ungerer #define MCFINT_UART0 26 /* Interrupt number for UART0 */ 206eac4027SGreg Ungerer #define MCFINT_UART1 27 /* Interrupt number for UART1 */ 216eac4027SGreg Ungerer #define MCFINT_UART2 28 /* Interrupt number for UART2 */ 222d24b532SSteven King #define MCFINT_I2C0 30 /* Interrupt number for I2C */ 236eac4027SGreg Ungerer #define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 246eac4027SGreg Ungerer #define MCFINT_FECRX0 36 /* Interrupt number for FEC */ 256eac4027SGreg Ungerer #define MCFINT_FECTX0 40 /* Interrupt number for FEC */ 266eac4027SGreg Ungerer #define MCFINT_FECENTC0 42 /* Interrupt number for FEC */ 276eac4027SGreg Ungerer 286eac4027SGreg Ungerer #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) 296eac4027SGreg Ungerer #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) 306eac4027SGreg Ungerer #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) 316eac4027SGreg Ungerer 326eac4027SGreg Ungerer #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) 336eac4027SGreg Ungerer #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) 346eac4027SGreg Ungerer #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 356eac4027SGreg Ungerer 362d24b532SSteven King #define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0) 376eac4027SGreg Ungerer #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 386eac4027SGreg Ungerer 396eac4027SGreg Ungerer #define MCF_WTM_WCR 0xFC098000 406eac4027SGreg Ungerer 416eac4027SGreg Ungerer /* 426eac4027SGreg Ungerer * Define the 532x SIM register set addresses. 436eac4027SGreg Ungerer */ 446eac4027SGreg Ungerer #define MCFSIM_IPRL 0xFC048004 456eac4027SGreg Ungerer #define MCFSIM_IPRH 0xFC048000 466eac4027SGreg Ungerer #define MCFSIM_IPR MCFSIM_IPRL 476eac4027SGreg Ungerer #define MCFSIM_IMRL 0xFC04800C 486eac4027SGreg Ungerer #define MCFSIM_IMRH 0xFC048008 496eac4027SGreg Ungerer #define MCFSIM_IMR MCFSIM_IMRL 506eac4027SGreg Ungerer #define MCFSIM_ICR0 0xFC048040 516eac4027SGreg Ungerer #define MCFSIM_ICR1 0xFC048041 526eac4027SGreg Ungerer #define MCFSIM_ICR2 0xFC048042 536eac4027SGreg Ungerer #define MCFSIM_ICR3 0xFC048043 546eac4027SGreg Ungerer #define MCFSIM_ICR4 0xFC048044 556eac4027SGreg Ungerer #define MCFSIM_ICR5 0xFC048045 566eac4027SGreg Ungerer #define MCFSIM_ICR6 0xFC048046 576eac4027SGreg Ungerer #define MCFSIM_ICR7 0xFC048047 586eac4027SGreg Ungerer #define MCFSIM_ICR8 0xFC048048 596eac4027SGreg Ungerer #define MCFSIM_ICR9 0xFC048049 606eac4027SGreg Ungerer #define MCFSIM_ICR10 0xFC04804A 616eac4027SGreg Ungerer #define MCFSIM_ICR11 0xFC04804B 626eac4027SGreg Ungerer 636eac4027SGreg Ungerer /* 646eac4027SGreg Ungerer * Some symbol defines for the above... 656eac4027SGreg Ungerer */ 666eac4027SGreg Ungerer #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ 676eac4027SGreg Ungerer #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ 686eac4027SGreg Ungerer #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ 696eac4027SGreg Ungerer #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ 706eac4027SGreg Ungerer #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ 716eac4027SGreg Ungerer #define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ 726eac4027SGreg Ungerer #define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ 736eac4027SGreg Ungerer #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ 746eac4027SGreg Ungerer #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 756eac4027SGreg Ungerer 766eac4027SGreg Ungerer 776eac4027SGreg Ungerer #define MCFINTC0_SIMR 0xFC04801C 786eac4027SGreg Ungerer #define MCFINTC0_CIMR 0xFC04801D 796eac4027SGreg Ungerer #define MCFINTC0_ICR0 0xFC048040 806eac4027SGreg Ungerer #define MCFINTC1_SIMR 0xFC04C01C 816eac4027SGreg Ungerer #define MCFINTC1_CIMR 0xFC04C01D 826eac4027SGreg Ungerer #define MCFINTC1_ICR0 0xFC04C040 836eac4027SGreg Ungerer #define MCFINTC2_SIMR (0) 846eac4027SGreg Ungerer #define MCFINTC2_CIMR (0) 856eac4027SGreg Ungerer #define MCFINTC2_ICR0 (0) 866eac4027SGreg Ungerer 876eac4027SGreg Ungerer #define MCFSIM_ICR_TIMER1 (0xFC048040+32) 886eac4027SGreg Ungerer #define MCFSIM_ICR_TIMER2 (0xFC048040+33) 896eac4027SGreg Ungerer 906eac4027SGreg Ungerer /* 916eac4027SGreg Ungerer * Define system peripheral IRQ usage. 926eac4027SGreg Ungerer */ 936eac4027SGreg Ungerer #define MCF_IRQ_TIMER (64 + 32) /* Timer0 */ 946eac4027SGreg Ungerer #define MCF_IRQ_PROFILER (64 + 33) /* Timer1 */ 956eac4027SGreg Ungerer 966eac4027SGreg Ungerer /* 976eac4027SGreg Ungerer * UART module. 986eac4027SGreg Ungerer */ 996eac4027SGreg Ungerer #define MCFUART_BASE0 0xFC060000 /* Base address of UART1 */ 1006eac4027SGreg Ungerer #define MCFUART_BASE1 0xFC064000 /* Base address of UART2 */ 1016eac4027SGreg Ungerer #define MCFUART_BASE2 0xFC068000 /* Base address of UART3 */ 1026eac4027SGreg Ungerer 1036eac4027SGreg Ungerer /* 1046eac4027SGreg Ungerer * FEC module. 1056eac4027SGreg Ungerer */ 1066eac4027SGreg Ungerer #define MCFFEC_BASE0 0xFC030000 /* Base address of FEC0 */ 1076eac4027SGreg Ungerer #define MCFFEC_SIZE0 0x800 /* Size of FEC0 region */ 1086eac4027SGreg Ungerer 1096eac4027SGreg Ungerer /* 1106eac4027SGreg Ungerer * QSPI module. 1116eac4027SGreg Ungerer */ 11242feae20SGreg Ungerer #define MCFQSPI_BASE 0xFC05C000 /* Base address of QSPI */ 1136eac4027SGreg Ungerer #define MCFQSPI_SIZE 0x40 /* Size of QSPI region */ 1146eac4027SGreg Ungerer 1156eac4027SGreg Ungerer #define MCFQSPI_CS0 84 1166eac4027SGreg Ungerer #define MCFQSPI_CS1 85 1176eac4027SGreg Ungerer #define MCFQSPI_CS2 86 1186eac4027SGreg Ungerer 1196eac4027SGreg Ungerer /* 1206eac4027SGreg Ungerer * Timer module. 1216eac4027SGreg Ungerer */ 1226eac4027SGreg Ungerer #define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */ 1236eac4027SGreg Ungerer #define MCFTIMER_BASE2 0xFC074000 /* Base address of TIMER2 */ 1246eac4027SGreg Ungerer #define MCFTIMER_BASE3 0xFC078000 /* Base address of TIMER3 */ 1256eac4027SGreg Ungerer #define MCFTIMER_BASE4 0xFC07C000 /* Base address of TIMER4 */ 1266eac4027SGreg Ungerer 1276eac4027SGreg Ungerer /********************************************************************* 1286eac4027SGreg Ungerer * 1296eac4027SGreg Ungerer * Reset Controller Module 1306eac4027SGreg Ungerer * 1316eac4027SGreg Ungerer *********************************************************************/ 1326eac4027SGreg Ungerer 1336eac4027SGreg Ungerer #define MCF_RCR 0xFC0A0000 1346eac4027SGreg Ungerer #define MCF_RSR 0xFC0A0001 1356eac4027SGreg Ungerer 1366eac4027SGreg Ungerer #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 1376eac4027SGreg Ungerer #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 1386eac4027SGreg Ungerer 1396eac4027SGreg Ungerer 1406eac4027SGreg Ungerer /* 1416eac4027SGreg Ungerer * Power Management 1426eac4027SGreg Ungerer */ 1436eac4027SGreg Ungerer #define MCFPM_WCR 0xfc040013 1446eac4027SGreg Ungerer #define MCFPM_PPMSR0 0xfc04002c 1456eac4027SGreg Ungerer #define MCFPM_PPMCR0 0xfc04002d 1466eac4027SGreg Ungerer #define MCFPM_PPMSR1 0xfc04002e 1476eac4027SGreg Ungerer #define MCFPM_PPMCR1 0xfc04002f 1486eac4027SGreg Ungerer #define MCFPM_PPMHR0 0xfc040030 1496eac4027SGreg Ungerer #define MCFPM_PPMLR0 0xfc040034 1506eac4027SGreg Ungerer #define MCFPM_PPMHR1 0xfc040038 1516eac4027SGreg Ungerer #define MCFPM_LPCR 0xec090007 1526eac4027SGreg Ungerer 1536eac4027SGreg Ungerer /* 1546eac4027SGreg Ungerer * The M5329EVB board needs a help getting its devices initialized 1556eac4027SGreg Ungerer * at kernel start time if dBUG doesn't set it up (for example 1566eac4027SGreg Ungerer * it is not used), so we need to do it manually. 1576eac4027SGreg Ungerer */ 1586eac4027SGreg Ungerer #ifdef __ASSEMBLER__ 1596eac4027SGreg Ungerer .macro m5329EVB_setup 1606eac4027SGreg Ungerer movel #0xFC098000, %a7 1616eac4027SGreg Ungerer movel #0x0, (%a7) 1626eac4027SGreg Ungerer #define CORE_SRAM 0x80000000 1636eac4027SGreg Ungerer #define CORE_SRAM_SIZE 0x8000 1646eac4027SGreg Ungerer movel #CORE_SRAM, %d0 1656eac4027SGreg Ungerer addl #0x221, %d0 1666eac4027SGreg Ungerer movec %d0,%RAMBAR1 1676eac4027SGreg Ungerer movel #CORE_SRAM, %sp 1686eac4027SGreg Ungerer addl #CORE_SRAM_SIZE, %sp 1696eac4027SGreg Ungerer jsr sysinit 1706eac4027SGreg Ungerer .endm 1716eac4027SGreg Ungerer #define PLATFORM_SETUP m5329EVB_setup 1726eac4027SGreg Ungerer 1736eac4027SGreg Ungerer #endif /* __ASSEMBLER__ */ 1746eac4027SGreg Ungerer 1756eac4027SGreg Ungerer /********************************************************************* 1766eac4027SGreg Ungerer * 1776eac4027SGreg Ungerer * Chip Configuration Module (CCM) 1786eac4027SGreg Ungerer * 1796eac4027SGreg Ungerer *********************************************************************/ 1806eac4027SGreg Ungerer 1816eac4027SGreg Ungerer /* Register read/write macros */ 1826eac4027SGreg Ungerer #define MCF_CCM_CCR 0xFC0A0004 1836eac4027SGreg Ungerer #define MCF_CCM_RCON 0xFC0A0008 1846eac4027SGreg Ungerer #define MCF_CCM_CIR 0xFC0A000A 1856eac4027SGreg Ungerer #define MCF_CCM_MISCCR 0xFC0A0010 1866eac4027SGreg Ungerer #define MCF_CCM_CDR 0xFC0A0012 1876eac4027SGreg Ungerer #define MCF_CCM_UHCSR 0xFC0A0014 1886eac4027SGreg Ungerer #define MCF_CCM_UOCSR 0xFC0A0016 1896eac4027SGreg Ungerer 1906eac4027SGreg Ungerer /* Bit definitions and macros for MCF_CCM_CCR */ 1916eac4027SGreg Ungerer #define MCF_CCM_CCR_RESERVED (0x0001) 1926eac4027SGreg Ungerer #define MCF_CCM_CCR_PLL_MODE (0x0003) 1936eac4027SGreg Ungerer #define MCF_CCM_CCR_OSC_MODE (0x0005) 1946eac4027SGreg Ungerer #define MCF_CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001) 1956eac4027SGreg Ungerer #define MCF_CCM_CCR_LOAD (0x0021) 1966eac4027SGreg Ungerer #define MCF_CCM_CCR_LIMP (0x0041) 1976eac4027SGreg Ungerer #define MCF_CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001) 1986eac4027SGreg Ungerer 1996eac4027SGreg Ungerer /* Bit definitions and macros for MCF_CCM_RCON */ 2006eac4027SGreg Ungerer #define MCF_CCM_RCON_RESERVED (0x0001) 2016eac4027SGreg Ungerer #define MCF_CCM_RCON_PLL_MODE (0x0003) 2026eac4027SGreg Ungerer #define MCF_CCM_RCON_OSC_MODE (0x0005) 2036eac4027SGreg Ungerer #define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001) 2046eac4027SGreg Ungerer #define MCF_CCM_RCON_LOAD (0x0021) 2056eac4027SGreg Ungerer #define MCF_CCM_RCON_LIMP (0x0041) 2066eac4027SGreg Ungerer #define MCF_CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001) 2076eac4027SGreg Ungerer 2086eac4027SGreg Ungerer /* Bit definitions and macros for MCF_CCM_CIR */ 2096eac4027SGreg Ungerer #define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0) 2106eac4027SGreg Ungerer #define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6) 2116eac4027SGreg Ungerer 2126eac4027SGreg Ungerer /* Bit definitions and macros for MCF_CCM_MISCCR */ 2136eac4027SGreg Ungerer #define MCF_CCM_MISCCR_USBSRC (0x0001) 2146eac4027SGreg Ungerer #define MCF_CCM_MISCCR_USBDIV (0x0002) 2156eac4027SGreg Ungerer #define MCF_CCM_MISCCR_SSI_SRC (0x0010) 2166eac4027SGreg Ungerer #define MCF_CCM_MISCCR_TIM_DMA (0x0020) 2176eac4027SGreg Ungerer #define MCF_CCM_MISCCR_SSI_PUS (0x0040) 2186eac4027SGreg Ungerer #define MCF_CCM_MISCCR_SSI_PUE (0x0080) 2196eac4027SGreg Ungerer #define MCF_CCM_MISCCR_LCD_CHEN (0x0100) 2206eac4027SGreg Ungerer #define MCF_CCM_MISCCR_LIMP (0x1000) 2216eac4027SGreg Ungerer #define MCF_CCM_MISCCR_PLL_LOCK (0x2000) 2226eac4027SGreg Ungerer 2236eac4027SGreg Ungerer /* Bit definitions and macros for MCF_CCM_CDR */ 2246eac4027SGreg Ungerer #define MCF_CCM_CDR_SSIDIV(x) (((x)&0x000F)<<0) 2256eac4027SGreg Ungerer #define MCF_CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) 2266eac4027SGreg Ungerer 2276eac4027SGreg Ungerer /* Bit definitions and macros for MCF_CCM_UHCSR */ 2286eac4027SGreg Ungerer #define MCF_CCM_UHCSR_XPDE (0x0001) 2296eac4027SGreg Ungerer #define MCF_CCM_UHCSR_UHMIE (0x0002) 2306eac4027SGreg Ungerer #define MCF_CCM_UHCSR_WKUP (0x0004) 2316eac4027SGreg Ungerer #define MCF_CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14) 2326eac4027SGreg Ungerer 2336eac4027SGreg Ungerer /* Bit definitions and macros for MCF_CCM_UOCSR */ 2346eac4027SGreg Ungerer #define MCF_CCM_UOCSR_XPDE (0x0001) 2356eac4027SGreg Ungerer #define MCF_CCM_UOCSR_UOMIE (0x0002) 2366eac4027SGreg Ungerer #define MCF_CCM_UOCSR_WKUP (0x0004) 2376eac4027SGreg Ungerer #define MCF_CCM_UOCSR_PWRFLT (0x0008) 2386eac4027SGreg Ungerer #define MCF_CCM_UOCSR_SEND (0x0010) 2396eac4027SGreg Ungerer #define MCF_CCM_UOCSR_VVLD (0x0020) 2406eac4027SGreg Ungerer #define MCF_CCM_UOCSR_BVLD (0x0040) 2416eac4027SGreg Ungerer #define MCF_CCM_UOCSR_AVLD (0x0080) 2426eac4027SGreg Ungerer #define MCF_CCM_UOCSR_DPPU (0x0100) 2436eac4027SGreg Ungerer #define MCF_CCM_UOCSR_DCR_VBUS (0x0200) 2446eac4027SGreg Ungerer #define MCF_CCM_UOCSR_CRG_VBUS (0x0400) 2456eac4027SGreg Ungerer #define MCF_CCM_UOCSR_DRV_VBUS (0x0800) 2466eac4027SGreg Ungerer #define MCF_CCM_UOCSR_DMPD (0x1000) 2476eac4027SGreg Ungerer #define MCF_CCM_UOCSR_DPPD (0x2000) 2486eac4027SGreg Ungerer #define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14) 2496eac4027SGreg Ungerer 2506eac4027SGreg Ungerer /********************************************************************* 2516eac4027SGreg Ungerer * 2526eac4027SGreg Ungerer * FlexBus Chip Selects (FBCS) 2536eac4027SGreg Ungerer * 2546eac4027SGreg Ungerer *********************************************************************/ 2556eac4027SGreg Ungerer 2566eac4027SGreg Ungerer /* Register read/write macros */ 2576eac4027SGreg Ungerer #define MCF_FBCS0_CSAR 0xFC008000 2586eac4027SGreg Ungerer #define MCF_FBCS0_CSMR 0xFC008004 2596eac4027SGreg Ungerer #define MCF_FBCS0_CSCR 0xFC008008 2606eac4027SGreg Ungerer #define MCF_FBCS1_CSAR 0xFC00800C 2616eac4027SGreg Ungerer #define MCF_FBCS1_CSMR 0xFC008010 2626eac4027SGreg Ungerer #define MCF_FBCS1_CSCR 0xFC008014 2636eac4027SGreg Ungerer #define MCF_FBCS2_CSAR 0xFC008018 2646eac4027SGreg Ungerer #define MCF_FBCS2_CSMR 0xFC00801C 2656eac4027SGreg Ungerer #define MCF_FBCS2_CSCR 0xFC008020 2666eac4027SGreg Ungerer #define MCF_FBCS3_CSAR 0xFC008024 2676eac4027SGreg Ungerer #define MCF_FBCS3_CSMR 0xFC008028 2686eac4027SGreg Ungerer #define MCF_FBCS3_CSCR 0xFC00802C 2696eac4027SGreg Ungerer #define MCF_FBCS4_CSAR 0xFC008030 2706eac4027SGreg Ungerer #define MCF_FBCS4_CSMR 0xFC008034 2716eac4027SGreg Ungerer #define MCF_FBCS4_CSCR 0xFC008038 2726eac4027SGreg Ungerer #define MCF_FBCS5_CSAR 0xFC00803C 2736eac4027SGreg Ungerer #define MCF_FBCS5_CSMR 0xFC008040 2746eac4027SGreg Ungerer #define MCF_FBCS5_CSCR 0xFC008044 2756eac4027SGreg Ungerer 2766eac4027SGreg Ungerer /* Bit definitions and macros for MCF_FBCS_CSAR */ 2776eac4027SGreg Ungerer #define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) 2786eac4027SGreg Ungerer 2796eac4027SGreg Ungerer /* Bit definitions and macros for MCF_FBCS_CSMR */ 2806eac4027SGreg Ungerer #define MCF_FBCS_CSMR_V (0x00000001) 2816eac4027SGreg Ungerer #define MCF_FBCS_CSMR_WP (0x00000100) 2826eac4027SGreg Ungerer #define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) 2836eac4027SGreg Ungerer #define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) 2846eac4027SGreg Ungerer #define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) 2856eac4027SGreg Ungerer #define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) 2866eac4027SGreg Ungerer #define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) 2876eac4027SGreg Ungerer #define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) 2886eac4027SGreg Ungerer #define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000) 2896eac4027SGreg Ungerer #define MCF_FBCS_CSMR_BAM_128M (0x07FF0000) 2906eac4027SGreg Ungerer #define MCF_FBCS_CSMR_BAM_64M (0x03FF0000) 2916eac4027SGreg Ungerer #define MCF_FBCS_CSMR_BAM_32M (0x01FF0000) 2926eac4027SGreg Ungerer #define MCF_FBCS_CSMR_BAM_16M (0x00FF0000) 2936eac4027SGreg Ungerer #define MCF_FBCS_CSMR_BAM_8M (0x007F0000) 2946eac4027SGreg Ungerer #define MCF_FBCS_CSMR_BAM_4M (0x003F0000) 2956eac4027SGreg Ungerer #define MCF_FBCS_CSMR_BAM_2M (0x001F0000) 2966eac4027SGreg Ungerer #define MCF_FBCS_CSMR_BAM_1M (0x000F0000) 2976eac4027SGreg Ungerer #define MCF_FBCS_CSMR_BAM_1024K (0x000F0000) 2986eac4027SGreg Ungerer #define MCF_FBCS_CSMR_BAM_512K (0x00070000) 2996eac4027SGreg Ungerer #define MCF_FBCS_CSMR_BAM_256K (0x00030000) 3006eac4027SGreg Ungerer #define MCF_FBCS_CSMR_BAM_128K (0x00010000) 3016eac4027SGreg Ungerer #define MCF_FBCS_CSMR_BAM_64K (0x00000000) 3026eac4027SGreg Ungerer 3036eac4027SGreg Ungerer /* Bit definitions and macros for MCF_FBCS_CSCR */ 3046eac4027SGreg Ungerer #define MCF_FBCS_CSCR_BSTW (0x00000008) 3056eac4027SGreg Ungerer #define MCF_FBCS_CSCR_BSTR (0x00000010) 3066eac4027SGreg Ungerer #define MCF_FBCS_CSCR_BEM (0x00000020) 3076eac4027SGreg Ungerer #define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) 3086eac4027SGreg Ungerer #define MCF_FBCS_CSCR_AA (0x00000100) 3096eac4027SGreg Ungerer #define MCF_FBCS_CSCR_SBM (0x00000200) 3106eac4027SGreg Ungerer #define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) 3116eac4027SGreg Ungerer #define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) 3126eac4027SGreg Ungerer #define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) 3136eac4027SGreg Ungerer #define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) 3146eac4027SGreg Ungerer #define MCF_FBCS_CSCR_SWSEN (0x00800000) 3156eac4027SGreg Ungerer #define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) 3166eac4027SGreg Ungerer #define MCF_FBCS_CSCR_PS_8 (0x0040) 3176eac4027SGreg Ungerer #define MCF_FBCS_CSCR_PS_16 (0x0080) 3186eac4027SGreg Ungerer #define MCF_FBCS_CSCR_PS_32 (0x0000) 3196eac4027SGreg Ungerer 3206eac4027SGreg Ungerer /********************************************************************* 3216eac4027SGreg Ungerer * 3226eac4027SGreg Ungerer * General Purpose I/O (GPIO) 3236eac4027SGreg Ungerer * 3246eac4027SGreg Ungerer *********************************************************************/ 3256eac4027SGreg Ungerer 3266eac4027SGreg Ungerer /* Register read/write macros */ 3276eac4027SGreg Ungerer #define MCFGPIO_PODR_FECH (0xFC0A4000) 3286eac4027SGreg Ungerer #define MCFGPIO_PODR_FECL (0xFC0A4001) 3296eac4027SGreg Ungerer #define MCFGPIO_PODR_SSI (0xFC0A4002) 3306eac4027SGreg Ungerer #define MCFGPIO_PODR_BUSCTL (0xFC0A4003) 3316eac4027SGreg Ungerer #define MCFGPIO_PODR_BE (0xFC0A4004) 3326eac4027SGreg Ungerer #define MCFGPIO_PODR_CS (0xFC0A4005) 3336eac4027SGreg Ungerer #define MCFGPIO_PODR_PWM (0xFC0A4006) 3346eac4027SGreg Ungerer #define MCFGPIO_PODR_FECI2C (0xFC0A4007) 3356eac4027SGreg Ungerer #define MCFGPIO_PODR_UART (0xFC0A4009) 3366eac4027SGreg Ungerer #define MCFGPIO_PODR_QSPI (0xFC0A400A) 3376eac4027SGreg Ungerer #define MCFGPIO_PODR_TIMER (0xFC0A400B) 3386eac4027SGreg Ungerer #define MCFGPIO_PODR_LCDDATAH (0xFC0A400D) 3396eac4027SGreg Ungerer #define MCFGPIO_PODR_LCDDATAM (0xFC0A400E) 3406eac4027SGreg Ungerer #define MCFGPIO_PODR_LCDDATAL (0xFC0A400F) 3416eac4027SGreg Ungerer #define MCFGPIO_PODR_LCDCTLH (0xFC0A4010) 3426eac4027SGreg Ungerer #define MCFGPIO_PODR_LCDCTLL (0xFC0A4011) 3436eac4027SGreg Ungerer #define MCFGPIO_PDDR_FECH (0xFC0A4014) 3446eac4027SGreg Ungerer #define MCFGPIO_PDDR_FECL (0xFC0A4015) 3456eac4027SGreg Ungerer #define MCFGPIO_PDDR_SSI (0xFC0A4016) 3466eac4027SGreg Ungerer #define MCFGPIO_PDDR_BUSCTL (0xFC0A4017) 3476eac4027SGreg Ungerer #define MCFGPIO_PDDR_BE (0xFC0A4018) 3486eac4027SGreg Ungerer #define MCFGPIO_PDDR_CS (0xFC0A4019) 3496eac4027SGreg Ungerer #define MCFGPIO_PDDR_PWM (0xFC0A401A) 3506eac4027SGreg Ungerer #define MCFGPIO_PDDR_FECI2C (0xFC0A401B) 3516eac4027SGreg Ungerer #define MCFGPIO_PDDR_UART (0xFC0A401C) 3526eac4027SGreg Ungerer #define MCFGPIO_PDDR_QSPI (0xFC0A401E) 3536eac4027SGreg Ungerer #define MCFGPIO_PDDR_TIMER (0xFC0A401F) 3546eac4027SGreg Ungerer #define MCFGPIO_PDDR_LCDDATAH (0xFC0A4021) 3556eac4027SGreg Ungerer #define MCFGPIO_PDDR_LCDDATAM (0xFC0A4022) 3566eac4027SGreg Ungerer #define MCFGPIO_PDDR_LCDDATAL (0xFC0A4023) 3576eac4027SGreg Ungerer #define MCFGPIO_PDDR_LCDCTLH (0xFC0A4024) 3586eac4027SGreg Ungerer #define MCFGPIO_PDDR_LCDCTLL (0xFC0A4025) 3596eac4027SGreg Ungerer #define MCFGPIO_PPDSDR_FECH (0xFC0A4028) 3606eac4027SGreg Ungerer #define MCFGPIO_PPDSDR_FECL (0xFC0A4029) 3616eac4027SGreg Ungerer #define MCFGPIO_PPDSDR_SSI (0xFC0A402A) 3626eac4027SGreg Ungerer #define MCFGPIO_PPDSDR_BUSCTL (0xFC0A402B) 3636eac4027SGreg Ungerer #define MCFGPIO_PPDSDR_BE (0xFC0A402C) 3646eac4027SGreg Ungerer #define MCFGPIO_PPDSDR_CS (0xFC0A402D) 3656eac4027SGreg Ungerer #define MCFGPIO_PPDSDR_PWM (0xFC0A402E) 3666eac4027SGreg Ungerer #define MCFGPIO_PPDSDR_FECI2C (0xFC0A402F) 3676eac4027SGreg Ungerer #define MCFGPIO_PPDSDR_UART (0xFC0A4031) 3686eac4027SGreg Ungerer #define MCFGPIO_PPDSDR_QSPI (0xFC0A4032) 3696eac4027SGreg Ungerer #define MCFGPIO_PPDSDR_TIMER (0xFC0A4033) 3706eac4027SGreg Ungerer #define MCFGPIO_PPDSDR_LCDDATAH (0xFC0A4035) 3716eac4027SGreg Ungerer #define MCFGPIO_PPDSDR_LCDDATAM (0xFC0A4036) 3726eac4027SGreg Ungerer #define MCFGPIO_PPDSDR_LCDDATAL (0xFC0A4037) 3736eac4027SGreg Ungerer #define MCFGPIO_PPDSDR_LCDCTLH (0xFC0A4038) 3746eac4027SGreg Ungerer #define MCFGPIO_PPDSDR_LCDCTLL (0xFC0A4039) 3756eac4027SGreg Ungerer #define MCFGPIO_PCLRR_FECH (0xFC0A403C) 3766eac4027SGreg Ungerer #define MCFGPIO_PCLRR_FECL (0xFC0A403D) 3776eac4027SGreg Ungerer #define MCFGPIO_PCLRR_SSI (0xFC0A403E) 3786eac4027SGreg Ungerer #define MCFGPIO_PCLRR_BUSCTL (0xFC0A403F) 3796eac4027SGreg Ungerer #define MCFGPIO_PCLRR_BE (0xFC0A4040) 3806eac4027SGreg Ungerer #define MCFGPIO_PCLRR_CS (0xFC0A4041) 3816eac4027SGreg Ungerer #define MCFGPIO_PCLRR_PWM (0xFC0A4042) 3826eac4027SGreg Ungerer #define MCFGPIO_PCLRR_FECI2C (0xFC0A4043) 3836eac4027SGreg Ungerer #define MCFGPIO_PCLRR_UART (0xFC0A4045) 3846eac4027SGreg Ungerer #define MCFGPIO_PCLRR_QSPI (0xFC0A4046) 3856eac4027SGreg Ungerer #define MCFGPIO_PCLRR_TIMER (0xFC0A4047) 3866eac4027SGreg Ungerer #define MCFGPIO_PCLRR_LCDDATAH (0xFC0A4049) 3876eac4027SGreg Ungerer #define MCFGPIO_PCLRR_LCDDATAM (0xFC0A404A) 3886eac4027SGreg Ungerer #define MCFGPIO_PCLRR_LCDDATAL (0xFC0A404B) 3896eac4027SGreg Ungerer #define MCFGPIO_PCLRR_LCDCTLH (0xFC0A404C) 3906eac4027SGreg Ungerer #define MCFGPIO_PCLRR_LCDCTLL (0xFC0A404D) 3916eac4027SGreg Ungerer #define MCFGPIO_PAR_FEC (0xFC0A4050) 3926eac4027SGreg Ungerer #define MCFGPIO_PAR_PWM (0xFC0A4051) 3936eac4027SGreg Ungerer #define MCFGPIO_PAR_BUSCTL (0xFC0A4052) 3946eac4027SGreg Ungerer #define MCFGPIO_PAR_FECI2C (0xFC0A4053) 3956eac4027SGreg Ungerer #define MCFGPIO_PAR_BE (0xFC0A4054) 3966eac4027SGreg Ungerer #define MCFGPIO_PAR_CS (0xFC0A4055) 3976eac4027SGreg Ungerer #define MCFGPIO_PAR_SSI (0xFC0A4056) 3986eac4027SGreg Ungerer #define MCFGPIO_PAR_UART (0xFC0A4058) 3996eac4027SGreg Ungerer #define MCFGPIO_PAR_QSPI (0xFC0A405A) 4006eac4027SGreg Ungerer #define MCFGPIO_PAR_TIMER (0xFC0A405C) 4016eac4027SGreg Ungerer #define MCFGPIO_PAR_LCDDATA (0xFC0A405D) 4026eac4027SGreg Ungerer #define MCFGPIO_PAR_LCDCTL (0xFC0A405E) 4036eac4027SGreg Ungerer #define MCFGPIO_PAR_IRQ (0xFC0A4060) 4046eac4027SGreg Ungerer #define MCFGPIO_MSCR_FLEXBUS (0xFC0A4064) 4056eac4027SGreg Ungerer #define MCFGPIO_MSCR_SDRAM (0xFC0A4065) 4066eac4027SGreg Ungerer #define MCFGPIO_DSCR_I2C (0xFC0A4068) 4076eac4027SGreg Ungerer #define MCFGPIO_DSCR_PWM (0xFC0A4069) 4086eac4027SGreg Ungerer #define MCFGPIO_DSCR_FEC (0xFC0A406A) 4096eac4027SGreg Ungerer #define MCFGPIO_DSCR_UART (0xFC0A406B) 4106eac4027SGreg Ungerer #define MCFGPIO_DSCR_QSPI (0xFC0A406C) 4116eac4027SGreg Ungerer #define MCFGPIO_DSCR_TIMER (0xFC0A406D) 4126eac4027SGreg Ungerer #define MCFGPIO_DSCR_SSI (0xFC0A406E) 4136eac4027SGreg Ungerer #define MCFGPIO_DSCR_LCD (0xFC0A406F) 4146eac4027SGreg Ungerer #define MCFGPIO_DSCR_DEBUG (0xFC0A4070) 4156eac4027SGreg Ungerer #define MCFGPIO_DSCR_CLKRST (0xFC0A4071) 4166eac4027SGreg Ungerer #define MCFGPIO_DSCR_IRQ (0xFC0A4072) 4176eac4027SGreg Ungerer 4186eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PODR_FECH */ 4196eac4027SGreg Ungerer #define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01) 4206eac4027SGreg Ungerer #define MCF_GPIO_PODR_FECH_PODR_FECH1 (0x02) 4216eac4027SGreg Ungerer #define MCF_GPIO_PODR_FECH_PODR_FECH2 (0x04) 4226eac4027SGreg Ungerer #define MCF_GPIO_PODR_FECH_PODR_FECH3 (0x08) 4236eac4027SGreg Ungerer #define MCF_GPIO_PODR_FECH_PODR_FECH4 (0x10) 4246eac4027SGreg Ungerer #define MCF_GPIO_PODR_FECH_PODR_FECH5 (0x20) 4256eac4027SGreg Ungerer #define MCF_GPIO_PODR_FECH_PODR_FECH6 (0x40) 4266eac4027SGreg Ungerer #define MCF_GPIO_PODR_FECH_PODR_FECH7 (0x80) 4276eac4027SGreg Ungerer 4286eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PODR_FECL */ 4296eac4027SGreg Ungerer #define MCF_GPIO_PODR_FECL_PODR_FECL0 (0x01) 4306eac4027SGreg Ungerer #define MCF_GPIO_PODR_FECL_PODR_FECL1 (0x02) 4316eac4027SGreg Ungerer #define MCF_GPIO_PODR_FECL_PODR_FECL2 (0x04) 4326eac4027SGreg Ungerer #define MCF_GPIO_PODR_FECL_PODR_FECL3 (0x08) 4336eac4027SGreg Ungerer #define MCF_GPIO_PODR_FECL_PODR_FECL4 (0x10) 4346eac4027SGreg Ungerer #define MCF_GPIO_PODR_FECL_PODR_FECL5 (0x20) 4356eac4027SGreg Ungerer #define MCF_GPIO_PODR_FECL_PODR_FECL6 (0x40) 4366eac4027SGreg Ungerer #define MCF_GPIO_PODR_FECL_PODR_FECL7 (0x80) 4376eac4027SGreg Ungerer 4386eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PODR_SSI */ 4396eac4027SGreg Ungerer #define MCF_GPIO_PODR_SSI_PODR_SSI0 (0x01) 4406eac4027SGreg Ungerer #define MCF_GPIO_PODR_SSI_PODR_SSI1 (0x02) 4416eac4027SGreg Ungerer #define MCF_GPIO_PODR_SSI_PODR_SSI2 (0x04) 4426eac4027SGreg Ungerer #define MCF_GPIO_PODR_SSI_PODR_SSI3 (0x08) 4436eac4027SGreg Ungerer #define MCF_GPIO_PODR_SSI_PODR_SSI4 (0x10) 4446eac4027SGreg Ungerer 4456eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */ 4466eac4027SGreg Ungerer #define MCF_GPIO_PODR_BUSCTL_POSDR_BUSCTL0 (0x01) 4476eac4027SGreg Ungerer #define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02) 4486eac4027SGreg Ungerer #define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04) 4496eac4027SGreg Ungerer #define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08) 4506eac4027SGreg Ungerer 4516eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PODR_BE */ 4526eac4027SGreg Ungerer #define MCF_GPIO_PODR_BE_PODR_BE0 (0x01) 4536eac4027SGreg Ungerer #define MCF_GPIO_PODR_BE_PODR_BE1 (0x02) 4546eac4027SGreg Ungerer #define MCF_GPIO_PODR_BE_PODR_BE2 (0x04) 4556eac4027SGreg Ungerer #define MCF_GPIO_PODR_BE_PODR_BE3 (0x08) 4566eac4027SGreg Ungerer 4576eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PODR_CS */ 4586eac4027SGreg Ungerer #define MCF_GPIO_PODR_CS_PODR_CS1 (0x02) 4596eac4027SGreg Ungerer #define MCF_GPIO_PODR_CS_PODR_CS2 (0x04) 4606eac4027SGreg Ungerer #define MCF_GPIO_PODR_CS_PODR_CS3 (0x08) 4616eac4027SGreg Ungerer #define MCF_GPIO_PODR_CS_PODR_CS4 (0x10) 4626eac4027SGreg Ungerer #define MCF_GPIO_PODR_CS_PODR_CS5 (0x20) 4636eac4027SGreg Ungerer 4646eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PODR_PWM */ 4656eac4027SGreg Ungerer #define MCF_GPIO_PODR_PWM_PODR_PWM2 (0x04) 4666eac4027SGreg Ungerer #define MCF_GPIO_PODR_PWM_PODR_PWM3 (0x08) 4676eac4027SGreg Ungerer #define MCF_GPIO_PODR_PWM_PODR_PWM4 (0x10) 4686eac4027SGreg Ungerer #define MCF_GPIO_PODR_PWM_PODR_PWM5 (0x20) 4696eac4027SGreg Ungerer 4706eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ 4716eac4027SGreg Ungerer #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) 4726eac4027SGreg Ungerer #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) 4736eac4027SGreg Ungerer #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) 4746eac4027SGreg Ungerer #define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) 4756eac4027SGreg Ungerer 4766eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PODR_UART */ 4776eac4027SGreg Ungerer #define MCF_GPIO_PODR_UART_PODR_UART0 (0x01) 4786eac4027SGreg Ungerer #define MCF_GPIO_PODR_UART_PODR_UART1 (0x02) 4796eac4027SGreg Ungerer #define MCF_GPIO_PODR_UART_PODR_UART2 (0x04) 4806eac4027SGreg Ungerer #define MCF_GPIO_PODR_UART_PODR_UART3 (0x08) 4816eac4027SGreg Ungerer #define MCF_GPIO_PODR_UART_PODR_UART4 (0x10) 4826eac4027SGreg Ungerer #define MCF_GPIO_PODR_UART_PODR_UART5 (0x20) 4836eac4027SGreg Ungerer #define MCF_GPIO_PODR_UART_PODR_UART6 (0x40) 4846eac4027SGreg Ungerer #define MCF_GPIO_PODR_UART_PODR_UART7 (0x80) 4856eac4027SGreg Ungerer 4866eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PODR_QSPI */ 4876eac4027SGreg Ungerer #define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01) 4886eac4027SGreg Ungerer #define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02) 4896eac4027SGreg Ungerer #define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04) 4906eac4027SGreg Ungerer #define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08) 4916eac4027SGreg Ungerer #define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10) 4926eac4027SGreg Ungerer #define MCF_GPIO_PODR_QSPI_PODR_QSPI5 (0x20) 4936eac4027SGreg Ungerer 4946eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PODR_TIMER */ 4956eac4027SGreg Ungerer #define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01) 4966eac4027SGreg Ungerer #define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02) 4976eac4027SGreg Ungerer #define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04) 4986eac4027SGreg Ungerer #define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08) 4996eac4027SGreg Ungerer 5006eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAH */ 5016eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH0 (0x01) 5026eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH1 (0x02) 5036eac4027SGreg Ungerer 5046eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAM */ 5056eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM0 (0x01) 5066eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM1 (0x02) 5076eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM2 (0x04) 5086eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM3 (0x08) 5096eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM4 (0x10) 5106eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM5 (0x20) 5116eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM6 (0x40) 5126eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM7 (0x80) 5136eac4027SGreg Ungerer 5146eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAL */ 5156eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL0 (0x01) 5166eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL1 (0x02) 5176eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL2 (0x04) 5186eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL3 (0x08) 5196eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL4 (0x10) 5206eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL5 (0x20) 5216eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL6 (0x40) 5226eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL7 (0x80) 5236eac4027SGreg Ungerer 5246eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLH */ 5256eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDCTLH_PODR_LCDCTLH0 (0x01) 5266eac4027SGreg Ungerer 5276eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLL */ 5286eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL0 (0x01) 5296eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL1 (0x02) 5306eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL2 (0x04) 5316eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL3 (0x08) 5326eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL4 (0x10) 5336eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL5 (0x20) 5346eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL6 (0x40) 5356eac4027SGreg Ungerer #define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL7 (0x80) 5366eac4027SGreg Ungerer 5376eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PDDR_FECH */ 5386eac4027SGreg Ungerer #define MCF_GPIO_PDDR_FECH_PDDR_FECH0 (0x01) 5396eac4027SGreg Ungerer #define MCF_GPIO_PDDR_FECH_PDDR_FECH1 (0x02) 5406eac4027SGreg Ungerer #define MCF_GPIO_PDDR_FECH_PDDR_FECH2 (0x04) 5416eac4027SGreg Ungerer #define MCF_GPIO_PDDR_FECH_PDDR_FECH3 (0x08) 5426eac4027SGreg Ungerer #define MCF_GPIO_PDDR_FECH_PDDR_FECH4 (0x10) 5436eac4027SGreg Ungerer #define MCF_GPIO_PDDR_FECH_PDDR_FECH5 (0x20) 5446eac4027SGreg Ungerer #define MCF_GPIO_PDDR_FECH_PDDR_FECH6 (0x40) 5456eac4027SGreg Ungerer #define MCF_GPIO_PDDR_FECH_PDDR_FECH7 (0x80) 5466eac4027SGreg Ungerer 5476eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PDDR_FECL */ 5486eac4027SGreg Ungerer #define MCF_GPIO_PDDR_FECL_PDDR_FECL0 (0x01) 5496eac4027SGreg Ungerer #define MCF_GPIO_PDDR_FECL_PDDR_FECL1 (0x02) 5506eac4027SGreg Ungerer #define MCF_GPIO_PDDR_FECL_PDDR_FECL2 (0x04) 5516eac4027SGreg Ungerer #define MCF_GPIO_PDDR_FECL_PDDR_FECL3 (0x08) 5526eac4027SGreg Ungerer #define MCF_GPIO_PDDR_FECL_PDDR_FECL4 (0x10) 5536eac4027SGreg Ungerer #define MCF_GPIO_PDDR_FECL_PDDR_FECL5 (0x20) 5546eac4027SGreg Ungerer #define MCF_GPIO_PDDR_FECL_PDDR_FECL6 (0x40) 5556eac4027SGreg Ungerer #define MCF_GPIO_PDDR_FECL_PDDR_FECL7 (0x80) 5566eac4027SGreg Ungerer 5576eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PDDR_SSI */ 5586eac4027SGreg Ungerer #define MCF_GPIO_PDDR_SSI_PDDR_SSI0 (0x01) 5596eac4027SGreg Ungerer #define MCF_GPIO_PDDR_SSI_PDDR_SSI1 (0x02) 5606eac4027SGreg Ungerer #define MCF_GPIO_PDDR_SSI_PDDR_SSI2 (0x04) 5616eac4027SGreg Ungerer #define MCF_GPIO_PDDR_SSI_PDDR_SSI3 (0x08) 5626eac4027SGreg Ungerer #define MCF_GPIO_PDDR_SSI_PDDR_SSI4 (0x10) 5636eac4027SGreg Ungerer 5646eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */ 5656eac4027SGreg Ungerer #define MCF_GPIO_PDDR_BUSCTL_POSDR_BUSCTL0 (0x01) 5666eac4027SGreg Ungerer #define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02) 5676eac4027SGreg Ungerer #define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04) 5686eac4027SGreg Ungerer #define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08) 5696eac4027SGreg Ungerer 5706eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PDDR_BE */ 5716eac4027SGreg Ungerer #define MCF_GPIO_PDDR_BE_PDDR_BE0 (0x01) 5726eac4027SGreg Ungerer #define MCF_GPIO_PDDR_BE_PDDR_BE1 (0x02) 5736eac4027SGreg Ungerer #define MCF_GPIO_PDDR_BE_PDDR_BE2 (0x04) 5746eac4027SGreg Ungerer #define MCF_GPIO_PDDR_BE_PDDR_BE3 (0x08) 5756eac4027SGreg Ungerer 5766eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PDDR_CS */ 5776eac4027SGreg Ungerer #define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02) 5786eac4027SGreg Ungerer #define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04) 5796eac4027SGreg Ungerer #define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08) 5806eac4027SGreg Ungerer #define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10) 5816eac4027SGreg Ungerer #define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20) 5826eac4027SGreg Ungerer 5836eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PDDR_PWM */ 5846eac4027SGreg Ungerer #define MCF_GPIO_PDDR_PWM_PDDR_PWM2 (0x04) 5856eac4027SGreg Ungerer #define MCF_GPIO_PDDR_PWM_PDDR_PWM3 (0x08) 5866eac4027SGreg Ungerer #define MCF_GPIO_PDDR_PWM_PDDR_PWM4 (0x10) 5876eac4027SGreg Ungerer #define MCF_GPIO_PDDR_PWM_PDDR_PWM5 (0x20) 5886eac4027SGreg Ungerer 5896eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ 5906eac4027SGreg Ungerer #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) 5916eac4027SGreg Ungerer #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) 5926eac4027SGreg Ungerer #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) 5936eac4027SGreg Ungerer #define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) 5946eac4027SGreg Ungerer 5956eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PDDR_UART */ 5966eac4027SGreg Ungerer #define MCF_GPIO_PDDR_UART_PDDR_UART0 (0x01) 5976eac4027SGreg Ungerer #define MCF_GPIO_PDDR_UART_PDDR_UART1 (0x02) 5986eac4027SGreg Ungerer #define MCF_GPIO_PDDR_UART_PDDR_UART2 (0x04) 5996eac4027SGreg Ungerer #define MCF_GPIO_PDDR_UART_PDDR_UART3 (0x08) 6006eac4027SGreg Ungerer #define MCF_GPIO_PDDR_UART_PDDR_UART4 (0x10) 6016eac4027SGreg Ungerer #define MCF_GPIO_PDDR_UART_PDDR_UART5 (0x20) 6026eac4027SGreg Ungerer #define MCF_GPIO_PDDR_UART_PDDR_UART6 (0x40) 6036eac4027SGreg Ungerer #define MCF_GPIO_PDDR_UART_PDDR_UART7 (0x80) 6046eac4027SGreg Ungerer 6056eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */ 6066eac4027SGreg Ungerer #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01) 6076eac4027SGreg Ungerer #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02) 6086eac4027SGreg Ungerer #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04) 6096eac4027SGreg Ungerer #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08) 6106eac4027SGreg Ungerer #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10) 6116eac4027SGreg Ungerer #define MCF_GPIO_PDDR_QSPI_PDDR_QSPI5 (0x20) 6126eac4027SGreg Ungerer 6136eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */ 6146eac4027SGreg Ungerer #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01) 6156eac4027SGreg Ungerer #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02) 6166eac4027SGreg Ungerer #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04) 6176eac4027SGreg Ungerer #define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08) 6186eac4027SGreg Ungerer 6196eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAH */ 6206eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH0 (0x01) 6216eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH1 (0x02) 6226eac4027SGreg Ungerer 6236eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAM */ 6246eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM0 (0x01) 6256eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM1 (0x02) 6266eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM2 (0x04) 6276eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM3 (0x08) 6286eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM4 (0x10) 6296eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM5 (0x20) 6306eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM6 (0x40) 6316eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM7 (0x80) 6326eac4027SGreg Ungerer 6336eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAL */ 6346eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL0 (0x01) 6356eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL1 (0x02) 6366eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL2 (0x04) 6376eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL3 (0x08) 6386eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL4 (0x10) 6396eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL5 (0x20) 6406eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL6 (0x40) 6416eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL7 (0x80) 6426eac4027SGreg Ungerer 6436eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLH */ 6446eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDCTLH_PDDR_LCDCTLH0 (0x01) 6456eac4027SGreg Ungerer 6466eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLL */ 6476eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL0 (0x01) 6486eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL1 (0x02) 6496eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL2 (0x04) 6506eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL3 (0x08) 6516eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL4 (0x10) 6526eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL5 (0x20) 6536eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL6 (0x40) 6546eac4027SGreg Ungerer #define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL7 (0x80) 6556eac4027SGreg Ungerer 6566eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PPDSDR_FECH */ 6576eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH0 (0x01) 6586eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH1 (0x02) 6596eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH2 (0x04) 6606eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH3 (0x08) 6616eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH4 (0x10) 6626eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH5 (0x20) 6636eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH6 (0x40) 6646eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH7 (0x80) 6656eac4027SGreg Ungerer 6666eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PPDSDR_FECL */ 6676eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL0 (0x01) 6686eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL1 (0x02) 6696eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL2 (0x04) 6706eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL3 (0x08) 6716eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL4 (0x10) 6726eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL5 (0x20) 6736eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL6 (0x40) 6746eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL7 (0x80) 6756eac4027SGreg Ungerer 6766eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PPDSDR_SSI */ 6776eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI0 (0x01) 6786eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI1 (0x02) 6796eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI2 (0x04) 6806eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI3 (0x08) 6816eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI4 (0x10) 6826eac4027SGreg Ungerer 6836eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */ 6846eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_BUSCTL_POSDR_BUSCTL0 (0x01) 6856eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02) 6866eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04) 6876eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08) 6886eac4027SGreg Ungerer 6896eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PPDSDR_BE */ 6906eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE0 (0x01) 6916eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE1 (0x02) 6926eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE2 (0x04) 6936eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_BE_PPDSDR_BE3 (0x08) 6946eac4027SGreg Ungerer 6956eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */ 6966eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02) 6976eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04) 6986eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08) 6996eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10) 7006eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20) 7016eac4027SGreg Ungerer 7026eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PPDSDR_PWM */ 7036eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM2 (0x04) 7046eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM3 (0x08) 7056eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM4 (0x10) 7066eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM5 (0x20) 7076eac4027SGreg Ungerer 7086eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ 7096eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) 7106eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) 7116eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) 7126eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) 7136eac4027SGreg Ungerer 7146eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PPDSDR_UART */ 7156eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART0 (0x01) 7166eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART1 (0x02) 7176eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART2 (0x04) 7186eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART3 (0x08) 7196eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART4 (0x10) 7206eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART5 (0x20) 7216eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART6 (0x40) 7226eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_UART_PPDSDR_UART7 (0x80) 7236eac4027SGreg Ungerer 7246eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */ 7256eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01) 7266eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02) 7276eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04) 7286eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08) 7296eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10) 7306eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI5 (0x20) 7316eac4027SGreg Ungerer 7326eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */ 7336eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01) 7346eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02) 7356eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04) 7366eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08) 7376eac4027SGreg Ungerer 7386eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAH */ 7396eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH0 (0x01) 7406eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH1 (0x02) 7416eac4027SGreg Ungerer 7426eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAM */ 7436eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM0 (0x01) 7446eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM1 (0x02) 7456eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM2 (0x04) 7466eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM3 (0x08) 7476eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM4 (0x10) 7486eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM5 (0x20) 7496eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM6 (0x40) 7506eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM7 (0x80) 7516eac4027SGreg Ungerer 7526eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAL */ 7536eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL0 (0x01) 7546eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL1 (0x02) 7556eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL2 (0x04) 7566eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL3 (0x08) 7576eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL4 (0x10) 7586eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL5 (0x20) 7596eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL6 (0x40) 7606eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL7 (0x80) 7616eac4027SGreg Ungerer 7626eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLH */ 7636eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDCTLH_PPDSDR_LCDCTLH0 (0x01) 7646eac4027SGreg Ungerer 7656eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLL */ 7666eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL0 (0x01) 7676eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL1 (0x02) 7686eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL2 (0x04) 7696eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL3 (0x08) 7706eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL4 (0x10) 7716eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL5 (0x20) 7726eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL6 (0x40) 7736eac4027SGreg Ungerer #define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL7 (0x80) 7746eac4027SGreg Ungerer 7756eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PCLRR_FECH */ 7766eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH0 (0x01) 7776eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH1 (0x02) 7786eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH2 (0x04) 7796eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH3 (0x08) 7806eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH4 (0x10) 7816eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH5 (0x20) 7826eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH6 (0x40) 7836eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_FECH_PCLRR_FECH7 (0x80) 7846eac4027SGreg Ungerer 7856eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PCLRR_FECL */ 7866eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL0 (0x01) 7876eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL1 (0x02) 7886eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL2 (0x04) 7896eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL3 (0x08) 7906eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL4 (0x10) 7916eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL5 (0x20) 7926eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL6 (0x40) 7936eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_FECL_PCLRR_FECL7 (0x80) 7946eac4027SGreg Ungerer 7956eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PCLRR_SSI */ 7966eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI0 (0x01) 7976eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI1 (0x02) 7986eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI2 (0x04) 7996eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI3 (0x08) 8006eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_SSI_PCLRR_SSI4 (0x10) 8016eac4027SGreg Ungerer 8026eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */ 8036eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_BUSCTL_POSDR_BUSCTL0 (0x01) 8046eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02) 8056eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04) 8066eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08) 8076eac4027SGreg Ungerer 8086eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PCLRR_BE */ 8096eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_BE_PCLRR_BE0 (0x01) 8106eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_BE_PCLRR_BE1 (0x02) 8116eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_BE_PCLRR_BE2 (0x04) 8126eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_BE_PCLRR_BE3 (0x08) 8136eac4027SGreg Ungerer 8146eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PCLRR_CS */ 8156eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02) 8166eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04) 8176eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08) 8186eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10) 8196eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20) 8206eac4027SGreg Ungerer 8216eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PCLRR_PWM */ 8226eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM2 (0x04) 8236eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM3 (0x08) 8246eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM4 (0x10) 8256eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_PWM_PCLRR_PWM5 (0x20) 8266eac4027SGreg Ungerer 8276eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ 8286eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) 8296eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) 8306eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04) 8316eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) 8326eac4027SGreg Ungerer 8336eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PCLRR_UART */ 8346eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_UART_PCLRR_UART0 (0x01) 8356eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_UART_PCLRR_UART1 (0x02) 8366eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_UART_PCLRR_UART2 (0x04) 8376eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_UART_PCLRR_UART3 (0x08) 8386eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_UART_PCLRR_UART4 (0x10) 8396eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_UART_PCLRR_UART5 (0x20) 8406eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_UART_PCLRR_UART6 (0x40) 8416eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_UART_PCLRR_UART7 (0x80) 8426eac4027SGreg Ungerer 8436eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */ 8446eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01) 8456eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02) 8466eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04) 8476eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08) 8486eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10) 8496eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI5 (0x20) 8506eac4027SGreg Ungerer 8516eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */ 8526eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01) 8536eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02) 8546eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04) 8556eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08) 8566eac4027SGreg Ungerer 8576eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAH */ 8586eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH0 (0x01) 8596eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH1 (0x02) 8606eac4027SGreg Ungerer 8616eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAM */ 8626eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM0 (0x01) 8636eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM1 (0x02) 8646eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM2 (0x04) 8656eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM3 (0x08) 8666eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM4 (0x10) 8676eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM5 (0x20) 8686eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM6 (0x40) 8696eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM7 (0x80) 8706eac4027SGreg Ungerer 8716eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAL */ 8726eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL0 (0x01) 8736eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL1 (0x02) 8746eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL2 (0x04) 8756eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL3 (0x08) 8766eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL4 (0x10) 8776eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL5 (0x20) 8786eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL6 (0x40) 8796eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL7 (0x80) 8806eac4027SGreg Ungerer 8816eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLH */ 8826eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01) 8836eac4027SGreg Ungerer 8846eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLL */ 8856eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL0 (0x01) 8866eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL1 (0x02) 8876eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL2 (0x04) 8886eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL3 (0x08) 8896eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL4 (0x10) 8906eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL5 (0x20) 8916eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL6 (0x40) 8926eac4027SGreg Ungerer #define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL7 (0x80) 8936eac4027SGreg Ungerer 8946eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PAR_FEC */ 8956eac4027SGreg Ungerer #define MCF_GPIO_PAR_FEC_PAR_FEC_MII(x) (((x)&0x03)<<0) 8966eac4027SGreg Ungerer #define MCF_GPIO_PAR_FEC_PAR_FEC_7W(x) (((x)&0x03)<<2) 8976eac4027SGreg Ungerer #define MCF_GPIO_PAR_FEC_PAR_FEC_7W_GPIO (0x00) 8986eac4027SGreg Ungerer #define MCF_GPIO_PAR_FEC_PAR_FEC_7W_URTS1 (0x04) 8996eac4027SGreg Ungerer #define MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC (0x0C) 9006eac4027SGreg Ungerer #define MCF_GPIO_PAR_FEC_PAR_FEC_MII_GPIO (0x00) 9016eac4027SGreg Ungerer #define MCF_GPIO_PAR_FEC_PAR_FEC_MII_UART (0x01) 9026eac4027SGreg Ungerer #define MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC (0x03) 9036eac4027SGreg Ungerer 9046eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PAR_PWM */ 9056eac4027SGreg Ungerer #define MCF_GPIO_PAR_PWM_PAR_PWM1(x) (((x)&0x03)<<0) 9066eac4027SGreg Ungerer #define MCF_GPIO_PAR_PWM_PAR_PWM3(x) (((x)&0x03)<<2) 9076eac4027SGreg Ungerer #define MCF_GPIO_PAR_PWM_PAR_PWM5 (0x10) 9086eac4027SGreg Ungerer #define MCF_GPIO_PAR_PWM_PAR_PWM7 (0x20) 9096eac4027SGreg Ungerer 9106eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */ 9116eac4027SGreg Ungerer #define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x03)<<3) 9126eac4027SGreg Ungerer #define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x20) 9136eac4027SGreg Ungerer #define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x40) 9146eac4027SGreg Ungerer #define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x80) 9156eac4027SGreg Ungerer #define MCF_GPIO_PAR_BUSCTL_PAR_OE_GPIO (0x00) 9166eac4027SGreg Ungerer #define MCF_GPIO_PAR_BUSCTL_PAR_OE_OE (0x80) 9176eac4027SGreg Ungerer #define MCF_GPIO_PAR_BUSCTL_PAR_TA_GPIO (0x00) 9186eac4027SGreg Ungerer #define MCF_GPIO_PAR_BUSCTL_PAR_TA_TA (0x40) 9196eac4027SGreg Ungerer #define MCF_GPIO_PAR_BUSCTL_PAR_RWB_GPIO (0x00) 9206eac4027SGreg Ungerer #define MCF_GPIO_PAR_BUSCTL_PAR_RWB_RWB (0x20) 9216eac4027SGreg Ungerer #define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x00) 9226eac4027SGreg Ungerer #define MCF_GPIO_PAR_BUSCTL_PAR_TS_DACK0 (0x10) 9236eac4027SGreg Ungerer #define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x18) 9246eac4027SGreg Ungerer 9256eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */ 9266eac4027SGreg Ungerer #define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0) 9276eac4027SGreg Ungerer #define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2) 9286eac4027SGreg Ungerer #define MCF_GPIO_PAR_FECI2C_PAR_MDIO(x) (((x)&0x03)<<4) 9296eac4027SGreg Ungerer #define MCF_GPIO_PAR_FECI2C_PAR_MDC(x) (((x)&0x03)<<6) 9306eac4027SGreg Ungerer #define MCF_GPIO_PAR_FECI2C_PAR_MDC_GPIO (0x00) 9316eac4027SGreg Ungerer #define MCF_GPIO_PAR_FECI2C_PAR_MDC_UTXD2 (0x40) 9326eac4027SGreg Ungerer #define MCF_GPIO_PAR_FECI2C_PAR_MDC_SCL (0x80) 9336eac4027SGreg Ungerer #define MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC (0xC0) 9346eac4027SGreg Ungerer #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_GPIO (0x00) 9356eac4027SGreg Ungerer #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_URXD2 (0x10) 9366eac4027SGreg Ungerer #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_SDA (0x20) 9376eac4027SGreg Ungerer #define MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO (0x30) 9386eac4027SGreg Ungerer #define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00) 9396eac4027SGreg Ungerer #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) 9406eac4027SGreg Ungerer #define MCF_GPIO_PAR_FECI2C_PAR_SCL_SCL (0x0C) 9416eac4027SGreg Ungerer #define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00) 9426eac4027SGreg Ungerer #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) 9436eac4027SGreg Ungerer #define MCF_GPIO_PAR_FECI2C_PAR_SDA_SDA (0x03) 9446eac4027SGreg Ungerer 9456eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PAR_BE */ 9466eac4027SGreg Ungerer #define MCF_GPIO_PAR_BE_PAR_BE0 (0x01) 9476eac4027SGreg Ungerer #define MCF_GPIO_PAR_BE_PAR_BE1 (0x02) 9486eac4027SGreg Ungerer #define MCF_GPIO_PAR_BE_PAR_BE2 (0x04) 9496eac4027SGreg Ungerer #define MCF_GPIO_PAR_BE_PAR_BE3 (0x08) 9506eac4027SGreg Ungerer 9516eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PAR_CS */ 9526eac4027SGreg Ungerer #define MCF_GPIO_PAR_CS_PAR_CS1 (0x02) 9536eac4027SGreg Ungerer #define MCF_GPIO_PAR_CS_PAR_CS2 (0x04) 9546eac4027SGreg Ungerer #define MCF_GPIO_PAR_CS_PAR_CS3 (0x08) 9556eac4027SGreg Ungerer #define MCF_GPIO_PAR_CS_PAR_CS4 (0x10) 9566eac4027SGreg Ungerer #define MCF_GPIO_PAR_CS_PAR_CS5 (0x20) 9576eac4027SGreg Ungerer #define MCF_GPIO_PAR_CS_PAR_CS_CS1_GPIO (0x00) 9586eac4027SGreg Ungerer #define MCF_GPIO_PAR_CS_PAR_CS_CS1_SDCS1 (0x01) 9596eac4027SGreg Ungerer #define MCF_GPIO_PAR_CS_PAR_CS_CS1_CS1 (0x03) 9606eac4027SGreg Ungerer 9616eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PAR_SSI */ 9626eac4027SGreg Ungerer #define MCF_GPIO_PAR_SSI_PAR_MCLK (0x0080) 9636eac4027SGreg Ungerer #define MCF_GPIO_PAR_SSI_PAR_TXD(x) (((x)&0x0003)<<8) 9646eac4027SGreg Ungerer #define MCF_GPIO_PAR_SSI_PAR_RXD(x) (((x)&0x0003)<<10) 9656eac4027SGreg Ungerer #define MCF_GPIO_PAR_SSI_PAR_FS(x) (((x)&0x0003)<<12) 9666eac4027SGreg Ungerer #define MCF_GPIO_PAR_SSI_PAR_BCLK(x) (((x)&0x0003)<<14) 9676eac4027SGreg Ungerer 9686eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PAR_UART */ 9696eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0001) 9706eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0002) 9716eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_URTS0 (0x0004) 9726eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_UCTS0 (0x0008) 9736eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_UTXD1(x) (((x)&0x0003)<<4) 9746eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_URXD1(x) (((x)&0x0003)<<6) 9756eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_URTS1(x) (((x)&0x0003)<<8) 9766eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_UCTS1(x) (((x)&0x0003)<<10) 9776eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_UCTS1_GPIO (0x0000) 9786eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK (0x0800) 9796eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_UCTS1_ULPI_D7 (0x0400) 9806eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_UCTS1_UCTS1 (0x0C00) 9816eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_URTS1_GPIO (0x0000) 9826eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS (0x0200) 9836eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_URTS1_ULPI_D6 (0x0100) 9846eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_URTS1_URTS1 (0x0300) 9856eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_URXD1_GPIO (0x0000) 9866eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD (0x0080) 9876eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_URXD1_ULPI_D5 (0x0040) 9886eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_URXD1_URXD1 (0x00C0) 9896eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_UTXD1_GPIO (0x0000) 9906eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD (0x0020) 9916eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_UTXD1_ULPI_D4 (0x0010) 9926eac4027SGreg Ungerer #define MCF_GPIO_PAR_UART_PAR_UTXD1_UTXD1 (0x0030) 9936eac4027SGreg Ungerer 9946eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PAR_QSPI */ 9956eac4027SGreg Ungerer #define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x0003)<<4) 9966eac4027SGreg Ungerer #define MCF_GPIO_PAR_QSPI_PAR_DOUT(x) (((x)&0x0003)<<6) 9976eac4027SGreg Ungerer #define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x0003)<<8) 9986eac4027SGreg Ungerer #define MCF_GPIO_PAR_QSPI_PAR_PCS0(x) (((x)&0x0003)<<10) 9996eac4027SGreg Ungerer #define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x0003)<<12) 10006eac4027SGreg Ungerer #define MCF_GPIO_PAR_QSPI_PAR_PCS2(x) (((x)&0x0003)<<14) 10016eac4027SGreg Ungerer 10026eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ 10036eac4027SGreg Ungerer #define MCF_GPIO_PAR_TIMER_PAR_TIN0(x) (((x)&0x03)<<0) 10046eac4027SGreg Ungerer #define MCF_GPIO_PAR_TIMER_PAR_TIN1(x) (((x)&0x03)<<2) 10056eac4027SGreg Ungerer #define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<4) 10066eac4027SGreg Ungerer #define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<6) 10076eac4027SGreg Ungerer #define MCF_GPIO_PAR_TIMER_PAR_TIN3_GPIO (0x00) 10086eac4027SGreg Ungerer #define MCF_GPIO_PAR_TIMER_PAR_TIN3_TOUT3 (0x80) 10096eac4027SGreg Ungerer #define MCF_GPIO_PAR_TIMER_PAR_TIN3_URXD2 (0x40) 10106eac4027SGreg Ungerer #define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN3 (0xC0) 10116eac4027SGreg Ungerer #define MCF_GPIO_PAR_TIMER_PAR_TIN2_GPIO (0x00) 10126eac4027SGreg Ungerer #define MCF_GPIO_PAR_TIMER_PAR_TIN2_TOUT2 (0x20) 10136eac4027SGreg Ungerer #define MCF_GPIO_PAR_TIMER_PAR_TIN2_UTXD2 (0x10) 10146eac4027SGreg Ungerer #define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN2 (0x30) 10156eac4027SGreg Ungerer #define MCF_GPIO_PAR_TIMER_PAR_TIN1_GPIO (0x00) 10166eac4027SGreg Ungerer #define MCF_GPIO_PAR_TIMER_PAR_TIN1_TOUT1 (0x08) 10176eac4027SGreg Ungerer #define MCF_GPIO_PAR_TIMER_PAR_TIN1_DACK1 (0x04) 10186eac4027SGreg Ungerer #define MCF_GPIO_PAR_TIMER_PAR_TIN1_TIN1 (0x0C) 10196eac4027SGreg Ungerer #define MCF_GPIO_PAR_TIMER_PAR_TIN0_GPIO (0x00) 10206eac4027SGreg Ungerer #define MCF_GPIO_PAR_TIMER_PAR_TIN0_TOUT0 (0x02) 10216eac4027SGreg Ungerer #define MCF_GPIO_PAR_TIMER_PAR_TIN0_DREQ0 (0x01) 10226eac4027SGreg Ungerer #define MCF_GPIO_PAR_TIMER_PAR_TIN0_TIN0 (0x03) 10236eac4027SGreg Ungerer 10246eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PAR_LCDDATA */ 10256eac4027SGreg Ungerer #define MCF_GPIO_PAR_LCDDATA_PAR_LD7_0(x) (((x)&0x03)<<0) 10266eac4027SGreg Ungerer #define MCF_GPIO_PAR_LCDDATA_PAR_LD15_8(x) (((x)&0x03)<<2) 10276eac4027SGreg Ungerer #define MCF_GPIO_PAR_LCDDATA_PAR_LD16(x) (((x)&0x03)<<4) 10286eac4027SGreg Ungerer #define MCF_GPIO_PAR_LCDDATA_PAR_LD17(x) (((x)&0x03)<<6) 10296eac4027SGreg Ungerer 10306eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PAR_LCDCTL */ 10316eac4027SGreg Ungerer #define MCF_GPIO_PAR_LCDCTL_PAR_CLS (0x0001) 10326eac4027SGreg Ungerer #define MCF_GPIO_PAR_LCDCTL_PAR_PS (0x0002) 10336eac4027SGreg Ungerer #define MCF_GPIO_PAR_LCDCTL_PAR_REV (0x0004) 10346eac4027SGreg Ungerer #define MCF_GPIO_PAR_LCDCTL_PAR_SPL_SPR (0x0008) 10356eac4027SGreg Ungerer #define MCF_GPIO_PAR_LCDCTL_PAR_CONTRAST (0x0010) 10366eac4027SGreg Ungerer #define MCF_GPIO_PAR_LCDCTL_PAR_LSCLK (0x0020) 10376eac4027SGreg Ungerer #define MCF_GPIO_PAR_LCDCTL_PAR_LP_HSYNC (0x0040) 10386eac4027SGreg Ungerer #define MCF_GPIO_PAR_LCDCTL_PAR_FLM_VSYNC (0x0080) 10396eac4027SGreg Ungerer #define MCF_GPIO_PAR_LCDCTL_PAR_ACD_OE (0x0100) 10406eac4027SGreg Ungerer 10416eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_PAR_IRQ */ 10426eac4027SGreg Ungerer #define MCF_GPIO_PAR_IRQ_PAR_IRQ1(x) (((x)&0x0003)<<4) 10436eac4027SGreg Ungerer #define MCF_GPIO_PAR_IRQ_PAR_IRQ2(x) (((x)&0x0003)<<6) 10446eac4027SGreg Ungerer #define MCF_GPIO_PAR_IRQ_PAR_IRQ4(x) (((x)&0x0003)<<8) 10456eac4027SGreg Ungerer #define MCF_GPIO_PAR_IRQ_PAR_IRQ5(x) (((x)&0x0003)<<10) 10466eac4027SGreg Ungerer #define MCF_GPIO_PAR_IRQ_PAR_IRQ6(x) (((x)&0x0003)<<12) 10476eac4027SGreg Ungerer 10486eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_MSCR_FLEXBUS */ 10496eac4027SGreg Ungerer #define MCF_GPIO_MSCR_FLEXBUS_MSCR_ADDRCTL(x) (((x)&0x03)<<0) 10506eac4027SGreg Ungerer #define MCF_GPIO_MSCR_FLEXBUS_MSCR_DLOWER(x) (((x)&0x03)<<2) 10516eac4027SGreg Ungerer #define MCF_GPIO_MSCR_FLEXBUS_MSCR_DUPPER(x) (((x)&0x03)<<4) 10526eac4027SGreg Ungerer 10536eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_MSCR_SDRAM */ 10546eac4027SGreg Ungerer #define MCF_GPIO_MSCR_SDRAM_MSCR_SDRAM(x) (((x)&0x03)<<0) 10556eac4027SGreg Ungerer #define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLK(x) (((x)&0x03)<<2) 10566eac4027SGreg Ungerer #define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLKB(x) (((x)&0x03)<<4) 10576eac4027SGreg Ungerer 10586eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_DSCR_I2C */ 10596eac4027SGreg Ungerer #define MCF_GPIO_DSCR_I2C_I2C_DSE(x) (((x)&0x03)<<0) 10606eac4027SGreg Ungerer 10616eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_DSCR_PWM */ 10626eac4027SGreg Ungerer #define MCF_GPIO_DSCR_PWM_PWM_DSE(x) (((x)&0x03)<<0) 10636eac4027SGreg Ungerer 10646eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_DSCR_FEC */ 10656eac4027SGreg Ungerer #define MCF_GPIO_DSCR_FEC_FEC_DSE(x) (((x)&0x03)<<0) 10666eac4027SGreg Ungerer 10676eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_DSCR_UART */ 10686eac4027SGreg Ungerer #define MCF_GPIO_DSCR_UART_UART0_DSE(x) (((x)&0x03)<<0) 10696eac4027SGreg Ungerer #define MCF_GPIO_DSCR_UART_UART1_DSE(x) (((x)&0x03)<<2) 10706eac4027SGreg Ungerer 10716eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */ 10726eac4027SGreg Ungerer #define MCF_GPIO_DSCR_QSPI_QSPI_DSE(x) (((x)&0x03)<<0) 10736eac4027SGreg Ungerer 10746eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */ 10756eac4027SGreg Ungerer #define MCF_GPIO_DSCR_TIMER_TIMER_DSE(x) (((x)&0x03)<<0) 10766eac4027SGreg Ungerer 10776eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_DSCR_SSI */ 10786eac4027SGreg Ungerer #define MCF_GPIO_DSCR_SSI_SSI_DSE(x) (((x)&0x03)<<0) 10796eac4027SGreg Ungerer 10806eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_DSCR_LCD */ 10816eac4027SGreg Ungerer #define MCF_GPIO_DSCR_LCD_LCD_DSE(x) (((x)&0x03)<<0) 10826eac4027SGreg Ungerer 10836eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_DSCR_DEBUG */ 10846eac4027SGreg Ungerer #define MCF_GPIO_DSCR_DEBUG_DEBUG_DSE(x) (((x)&0x03)<<0) 10856eac4027SGreg Ungerer 10866eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_DSCR_CLKRST */ 10876eac4027SGreg Ungerer #define MCF_GPIO_DSCR_CLKRST_CLKRST_DSE(x) (((x)&0x03)<<0) 10886eac4027SGreg Ungerer 10896eac4027SGreg Ungerer /* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */ 10906eac4027SGreg Ungerer #define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x) (((x)&0x03)<<0) 10916eac4027SGreg Ungerer 10926eac4027SGreg Ungerer /* 10936eac4027SGreg Ungerer * Generic GPIO support 10946eac4027SGreg Ungerer */ 10956eac4027SGreg Ungerer #define MCFGPIO_PODR MCFGPIO_PODR_FECH 10966eac4027SGreg Ungerer #define MCFGPIO_PDDR MCFGPIO_PDDR_FECH 10976eac4027SGreg Ungerer #define MCFGPIO_PPDR MCFGPIO_PPDSDR_FECH 10986eac4027SGreg Ungerer #define MCFGPIO_SETR MCFGPIO_PPDSDR_FECH 10996eac4027SGreg Ungerer #define MCFGPIO_CLRR MCFGPIO_PCLRR_FECH 11006eac4027SGreg Ungerer 11016eac4027SGreg Ungerer #define MCFGPIO_PIN_MAX 136 11026eac4027SGreg Ungerer #define MCFGPIO_IRQ_MAX 8 11036eac4027SGreg Ungerer #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 11046eac4027SGreg Ungerer 11056eac4027SGreg Ungerer /********************************************************************* 11066eac4027SGreg Ungerer * 11076eac4027SGreg Ungerer * Phase Locked Loop (PLL) 11086eac4027SGreg Ungerer * 11096eac4027SGreg Ungerer *********************************************************************/ 11106eac4027SGreg Ungerer 11116eac4027SGreg Ungerer /* Register read/write macros */ 11126eac4027SGreg Ungerer #define MCF_PLL_PODR 0xFC0C0000 11136eac4027SGreg Ungerer #define MCF_PLL_PLLCR 0xFC0C0004 11146eac4027SGreg Ungerer #define MCF_PLL_PMDR 0xFC0C0008 11156eac4027SGreg Ungerer #define MCF_PLL_PFDR 0xFC0C000C 11166eac4027SGreg Ungerer 11176eac4027SGreg Ungerer /* Bit definitions and macros for MCF_PLL_PODR */ 11186eac4027SGreg Ungerer #define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0) 11196eac4027SGreg Ungerer #define MCF_PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4) 11206eac4027SGreg Ungerer 11216eac4027SGreg Ungerer /* Bit definitions and macros for MCF_PLL_PLLCR */ 11226eac4027SGreg Ungerer #define MCF_PLL_PLLCR_DITHDEV(x) (((x)&0x07)<<0) 11236eac4027SGreg Ungerer #define MCF_PLL_PLLCR_DITHEN (0x80) 11246eac4027SGreg Ungerer 11256eac4027SGreg Ungerer /* Bit definitions and macros for MCF_PLL_PMDR */ 11266eac4027SGreg Ungerer #define MCF_PLL_PMDR_MODDIV(x) (((x)&0xFF)<<0) 11276eac4027SGreg Ungerer 11286eac4027SGreg Ungerer /* Bit definitions and macros for MCF_PLL_PFDR */ 11296eac4027SGreg Ungerer #define MCF_PLL_PFDR_MFD(x) (((x)&0xFF)<<0) 11306eac4027SGreg Ungerer 11316eac4027SGreg Ungerer /********************************************************************* 11326eac4027SGreg Ungerer * 11336eac4027SGreg Ungerer * System Control Module Registers (SCM) 11346eac4027SGreg Ungerer * 11356eac4027SGreg Ungerer *********************************************************************/ 11366eac4027SGreg Ungerer 11376eac4027SGreg Ungerer /* Register read/write macros */ 11386eac4027SGreg Ungerer #define MCF_SCM_MPR 0xFC000000 11396eac4027SGreg Ungerer #define MCF_SCM_PACRA 0xFC000020 11406eac4027SGreg Ungerer #define MCF_SCM_PACRB 0xFC000024 11416eac4027SGreg Ungerer #define MCF_SCM_PACRC 0xFC000028 11426eac4027SGreg Ungerer #define MCF_SCM_PACRD 0xFC00002C 11436eac4027SGreg Ungerer #define MCF_SCM_PACRE 0xFC000040 11446eac4027SGreg Ungerer #define MCF_SCM_PACRF 0xFC000044 11456eac4027SGreg Ungerer 11466eac4027SGreg Ungerer #define MCF_SCM_BCR 0xFC040024 11476eac4027SGreg Ungerer 11486eac4027SGreg Ungerer /********************************************************************* 11496eac4027SGreg Ungerer * 11506eac4027SGreg Ungerer * SDRAM Controller (SDRAMC) 11516eac4027SGreg Ungerer * 11526eac4027SGreg Ungerer *********************************************************************/ 11536eac4027SGreg Ungerer 11546eac4027SGreg Ungerer /* Register read/write macros */ 11556eac4027SGreg Ungerer #define MCF_SDRAMC_SDMR 0xFC0B8000 11566eac4027SGreg Ungerer #define MCF_SDRAMC_SDCR 0xFC0B8004 11576eac4027SGreg Ungerer #define MCF_SDRAMC_SDCFG1 0xFC0B8008 11586eac4027SGreg Ungerer #define MCF_SDRAMC_SDCFG2 0xFC0B800C 11596eac4027SGreg Ungerer #define MCF_SDRAMC_LIMP_FIX 0xFC0B8080 11606eac4027SGreg Ungerer #define MCF_SDRAMC_SDDS 0xFC0B8100 11616eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS0 0xFC0B8110 11626eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS1 0xFC0B8114 11636eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS2 0xFC0B8118 11646eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS3 0xFC0B811C 11656eac4027SGreg Ungerer 11666eac4027SGreg Ungerer /* Bit definitions and macros for MCF_SDRAMC_SDMR */ 11676eac4027SGreg Ungerer #define MCF_SDRAMC_SDMR_CMD (0x00010000) 11686eac4027SGreg Ungerer #define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) 11696eac4027SGreg Ungerer #define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30) 11706eac4027SGreg Ungerer #define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000) 11716eac4027SGreg Ungerer #define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000) 11726eac4027SGreg Ungerer 11736eac4027SGreg Ungerer /* Bit definitions and macros for MCF_SDRAMC_SDCR */ 11746eac4027SGreg Ungerer #define MCF_SDRAMC_SDCR_IPALL (0x00000002) 11756eac4027SGreg Ungerer #define MCF_SDRAMC_SDCR_IREF (0x00000004) 11766eac4027SGreg Ungerer #define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) 11776eac4027SGreg Ungerer #define MCF_SDRAMC_SDCR_PS(x) (((x)&0x00000003)<<12) 11786eac4027SGreg Ungerer #define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) 11796eac4027SGreg Ungerer #define MCF_SDRAMC_SDCR_OE_RULE (0x00400000) 11806eac4027SGreg Ungerer #define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) 11816eac4027SGreg Ungerer #define MCF_SDRAMC_SDCR_REF (0x10000000) 11826eac4027SGreg Ungerer #define MCF_SDRAMC_SDCR_DDR (0x20000000) 11836eac4027SGreg Ungerer #define MCF_SDRAMC_SDCR_CKE (0x40000000) 11846eac4027SGreg Ungerer #define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) 11856eac4027SGreg Ungerer #define MCF_SDRAMC_SDCR_PS_16 (0x00002000) 11866eac4027SGreg Ungerer #define MCF_SDRAMC_SDCR_PS_32 (0x00000000) 11876eac4027SGreg Ungerer 11886eac4027SGreg Ungerer /* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ 11896eac4027SGreg Ungerer #define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) 11906eac4027SGreg Ungerer #define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) 11916eac4027SGreg Ungerer #define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) 11926eac4027SGreg Ungerer #define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) 11936eac4027SGreg Ungerer #define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) 11946eac4027SGreg Ungerer #define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) 11956eac4027SGreg Ungerer #define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) 11966eac4027SGreg Ungerer 11976eac4027SGreg Ungerer /* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ 11986eac4027SGreg Ungerer #define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) 11996eac4027SGreg Ungerer #define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) 12006eac4027SGreg Ungerer #define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) 12016eac4027SGreg Ungerer #define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) 12026eac4027SGreg Ungerer 12036eac4027SGreg Ungerer /* Device Errata - LIMP mode work around */ 12046eac4027SGreg Ungerer #define MCF_SDRAMC_REFRESH (0x40000000) 12056eac4027SGreg Ungerer 12066eac4027SGreg Ungerer /* Bit definitions and macros for MCF_SDRAMC_SDDS */ 12076eac4027SGreg Ungerer #define MCF_SDRAMC_SDDS_SB_D(x) (((x)&0x00000003)<<0) 12086eac4027SGreg Ungerer #define MCF_SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2) 12096eac4027SGreg Ungerer #define MCF_SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4) 12106eac4027SGreg Ungerer #define MCF_SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6) 12116eac4027SGreg Ungerer #define MCF_SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8) 12126eac4027SGreg Ungerer 12136eac4027SGreg Ungerer /* Bit definitions and macros for MCF_SDRAMC_SDCS */ 12146eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)<<0) 12156eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20) 12166eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) 12176eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS_CSSZ_DIABLE (0x00000000) 12186eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) 12196eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) 12206eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) 12216eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) 12226eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) 12236eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) 12246eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) 12256eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) 12266eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) 12276eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) 12286eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) 12296eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) 12306eac4027SGreg Ungerer #define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) 12316eac4027SGreg Ungerer 12326eac4027SGreg Ungerer /* 12336eac4027SGreg Ungerer * Edge Port Module (EPORT) 12346eac4027SGreg Ungerer */ 12356eac4027SGreg Ungerer #define MCFEPORT_EPPAR (0xFC094000) 12366eac4027SGreg Ungerer #define MCFEPORT_EPDDR (0xFC094002) 12376eac4027SGreg Ungerer #define MCFEPORT_EPIER (0xFC094003) 12386eac4027SGreg Ungerer #define MCFEPORT_EPDR (0xFC094004) 12396eac4027SGreg Ungerer #define MCFEPORT_EPPDR (0xFC094005) 12406eac4027SGreg Ungerer #define MCFEPORT_EPFR (0xFC094006) 12416eac4027SGreg Ungerer 12422d24b532SSteven King /* 12432d24b532SSteven King * I2C Module 12442d24b532SSteven King */ 12452d24b532SSteven King #define MCFI2C_BASE0 (0xFc058000) 12462d24b532SSteven King #define MCFI2C_SIZE0 0x40 12472d24b532SSteven King 12486eac4027SGreg Ungerer /********************************************************************/ 12496eac4027SGreg Ungerer #endif /* m53xxsim_h */ 1250