149148020SSam Ravnborg /****************************************************************************/ 249148020SSam Ravnborg 349148020SSam Ravnborg /* 449148020SSam Ravnborg * m527xsim.h -- ColdFire 5270/5271 System Integration Module support. 549148020SSam Ravnborg * 649148020SSam Ravnborg * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com) 749148020SSam Ravnborg */ 849148020SSam Ravnborg 949148020SSam Ravnborg /****************************************************************************/ 1049148020SSam Ravnborg #ifndef m527xsim_h 1149148020SSam Ravnborg #define m527xsim_h 1249148020SSam Ravnborg /****************************************************************************/ 1349148020SSam Ravnborg 147fc82b65SGreg Ungerer #define CPU_NAME "COLDFIRE(m527x)" 15733f31b7SGreg Ungerer #define CPU_INSTR_PER_JIFFY 3 16ce3de78aSGreg Ungerer #define MCF_BUSCLK (MCF_CLK / 2) 177fc82b65SGreg Ungerer 18a12cf0a8SGreg Ungerer #include <asm/m52xxacr.h> 1949148020SSam Ravnborg 2049148020SSam Ravnborg /* 2149148020SSam Ravnborg * Define the 5270/5271 SIM register set addresses. 2249148020SSam Ravnborg */ 23254eef74SGreg Ungerer #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ 24254eef74SGreg Ungerer #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */ 25254eef74SGreg Ungerer 2649148020SSam Ravnborg #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 2749148020SSam Ravnborg #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 2849148020SSam Ravnborg #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 2949148020SSam Ravnborg #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 3049148020SSam Ravnborg #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 3149148020SSam Ravnborg #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 3249148020SSam Ravnborg #define MCFINTC_IRLR 0x18 /* */ 3349148020SSam Ravnborg #define MCFINTC_IACKL 0x19 /* */ 3449148020SSam Ravnborg #define MCFINTC_ICR0 0x40 /* Base ICR register */ 3549148020SSam Ravnborg 3649148020SSam Ravnborg #define MCFINT_VECBASE 64 /* Vector base number */ 3749148020SSam Ravnborg #define MCFINT_UART0 13 /* Interrupt number for UART0 */ 3849148020SSam Ravnborg #define MCFINT_UART1 14 /* Interrupt number for UART1 */ 3949148020SSam Ravnborg #define MCFINT_UART2 15 /* Interrupt number for UART2 */ 4091d60417SSteven King #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 4149148020SSam Ravnborg #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ 4249148020SSam Ravnborg 4349148020SSam Ravnborg /* 4449148020SSam Ravnborg * SDRAM configuration registers. 4549148020SSam Ravnborg */ 4649148020SSam Ravnborg #ifdef CONFIG_M5271 476a92e198SGreg Ungerer #define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */ 486a92e198SGreg Ungerer #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ 496a92e198SGreg Ungerer #define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */ 506a92e198SGreg Ungerer #define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */ 516a92e198SGreg Ungerer #define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */ 5249148020SSam Ravnborg #endif 5349148020SSam Ravnborg #ifdef CONFIG_M5275 546a92e198SGreg Ungerer #define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */ 556a92e198SGreg Ungerer #define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */ 566a92e198SGreg Ungerer #define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */ 576a92e198SGreg Ungerer #define MCFSIM_DCFG2 (MCF_IPSBAR + 0x4c) /* Configuration 2 */ 586a92e198SGreg Ungerer #define MCFSIM_DBAR0 (MCF_IPSBAR + 0x50) /* Base address 0 */ 596a92e198SGreg Ungerer #define MCFSIM_DMR0 (MCF_IPSBAR + 0x54) /* Address mask 0 */ 606a92e198SGreg Ungerer #define MCFSIM_DBAR1 (MCF_IPSBAR + 0x58) /* Base address 1 */ 616a92e198SGreg Ungerer #define MCFSIM_DMR1 (MCF_IPSBAR + 0x5c) /* Address mask 1 */ 6249148020SSam Ravnborg #endif 6349148020SSam Ravnborg 6457015421SGreg Ungerer /* 65babc08b7SGreg Ungerer * DMA unit base addresses. 66babc08b7SGreg Ungerer */ 67babc08b7SGreg Ungerer #define MCFDMA_BASE0 (MCF_IPSBAR + 0x100) 68babc08b7SGreg Ungerer #define MCFDMA_BASE1 (MCF_IPSBAR + 0x140) 69babc08b7SGreg Ungerer #define MCFDMA_BASE2 (MCF_IPSBAR + 0x180) 70babc08b7SGreg Ungerer #define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0) 71babc08b7SGreg Ungerer 72babc08b7SGreg Ungerer /* 7357015421SGreg Ungerer * UART module. 7457015421SGreg Ungerer */ 759a6b0c73SGreg Ungerer #define MCFUART_BASE1 (MCF_IPSBAR + 0x200) 769a6b0c73SGreg Ungerer #define MCFUART_BASE2 (MCF_IPSBAR + 0x240) 779a6b0c73SGreg Ungerer #define MCFUART_BASE3 (MCF_IPSBAR + 0x280) 789a6b0c73SGreg Ungerer 799a6b0c73SGreg Ungerer /* 809a6b0c73SGreg Ungerer * FEC ethernet module. 819a6b0c73SGreg Ungerer */ 829a6b0c73SGreg Ungerer #define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000) 839a6b0c73SGreg Ungerer #define MCFFEC_SIZE0 0x800 849a6b0c73SGreg Ungerer #define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800) 859a6b0c73SGreg Ungerer #define MCFFEC_SIZE1 0x800 86f1554da3Ssfking@fdwdc.com 87f1554da3Ssfking@fdwdc.com #ifdef CONFIG_M5271 88f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) 89f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) 90f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) 91f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003) 92f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004) 93f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005) 94f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006) 95f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007) 96f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008) 97f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009) 98f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A) 99f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B) 100f1554da3Ssfking@fdwdc.com 101f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010) 102f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011) 103f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012) 104f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013) 105f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014) 106f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015) 107f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016) 108f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017) 109f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018) 110f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019) 111f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A) 112f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B) 113f1554da3Ssfking@fdwdc.com 114f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020) 115f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021) 116f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022) 117f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023) 118f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024) 119f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025) 120f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026) 121f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027) 122f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028) 123f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029) 124f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A) 125f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B) 126f1554da3Ssfking@fdwdc.com 127f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030) 128f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031) 129f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032) 130f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033) 131f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034) 132f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035) 133f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036) 134f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037) 135f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038) 136f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039) 137f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A) 138f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B) 139f1554da3Ssfking@fdwdc.com 140f1554da3Ssfking@fdwdc.com /* 141f1554da3Ssfking@fdwdc.com * Generic GPIO support 142f1554da3Ssfking@fdwdc.com */ 143f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR MCFGPIO_PODR_ADDR 144f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR 145f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR 146f1554da3Ssfking@fdwdc.com #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR 147f1554da3Ssfking@fdwdc.com #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR 148f1554da3Ssfking@fdwdc.com 149f1554da3Ssfking@fdwdc.com #define MCFGPIO_PIN_MAX 100 150f1554da3Ssfking@fdwdc.com #define MCFGPIO_IRQ_MAX 8 151f1554da3Ssfking@fdwdc.com #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 15291d60417SSteven King 15391d60417SSteven King #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) 15491d60417SSteven King #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) 155f1554da3Ssfking@fdwdc.com #endif 156f1554da3Ssfking@fdwdc.com 157f1554da3Ssfking@fdwdc.com #ifdef CONFIG_M5275 158f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004) 159f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100005) 160f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100008) 161f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FEC0H (MCF_IPSBAR + 0x10000A) 162f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FEC0L (MCF_IPSBAR + 0x10000B) 163f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x10000C) 164f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000D) 165f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x10000E) 166f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMERH (MCF_IPSBAR + 0x10000F) 167f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMERL (MCF_IPSBAR + 0x100010) 168f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100011) 169f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FEC1H (MCF_IPSBAR + 0x100012) 170f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FEC1L (MCF_IPSBAR + 0x100013) 171f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100014) 172f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_IRQ (MCF_IPSBAR + 0x100015) 173f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_USBH (MCF_IPSBAR + 0x100016) 174f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_USBL (MCF_IPSBAR + 0x100017) 175f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100018) 176f1554da3Ssfking@fdwdc.com 177f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100020) 178f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100021) 179f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100024) 180f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FEC0H (MCF_IPSBAR + 0x100026) 181f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FEC0L (MCF_IPSBAR + 0x100027) 182f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100028) 183f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x100029) 184f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x10002A) 185f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMERH (MCF_IPSBAR + 0x10002B) 186f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMERL (MCF_IPSBAR + 0x10002C) 187f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x10002D) 188f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FEC1H (MCF_IPSBAR + 0x10002E) 189f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FEC1L (MCF_IPSBAR + 0x10002F) 190f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100030) 191f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_IRQ (MCF_IPSBAR + 0x100031) 192f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_USBH (MCF_IPSBAR + 0x100032) 193f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_USBL (MCF_IPSBAR + 0x100033) 194f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100034) 195f1554da3Ssfking@fdwdc.com 196f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x10003C) 197f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x10003D) 198f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100040) 199f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FEC0H (MCF_IPSBAR + 0x100042) 200f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FEC0L (MCF_IPSBAR + 0x100043) 201f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100044) 202f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x100045) 203f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100046) 204f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_TIMERH (MCF_IPSBAR + 0x100047) 205f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_TIMERL (MCF_IPSBAR + 0x100048) 206f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100049) 207f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FEC1H (MCF_IPSBAR + 0x10004A) 208f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FEC1L (MCF_IPSBAR + 0x10004B) 209f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x10004C) 210f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_IRQ (MCF_IPSBAR + 0x10004D) 211f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_USBH (MCF_IPSBAR + 0x10004E) 212f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_USBL (MCF_IPSBAR + 0x10004F) 213f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100050) 214f1554da3Ssfking@fdwdc.com 215f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100058) 216f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100059) 217f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x10005C) 218f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FEC0H (MCF_IPSBAR + 0x10005E) 219f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FEC0L (MCF_IPSBAR + 0x10005F) 220f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100060) 221f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x100061) 222f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100062) 223f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMERH (MCF_IPSBAR + 0x100063) 224f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMERL (MCF_IPSBAR + 0x100064) 225f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100065) 226f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FEC1H (MCF_IPSBAR + 0x100066) 227f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FEC1L (MCF_IPSBAR + 0x100067) 228f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100068) 229f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_IRQ (MCF_IPSBAR + 0x100069) 230f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_USBH (MCF_IPSBAR + 0x10006A) 231f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_USBL (MCF_IPSBAR + 0x10006B) 232f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x10006C) 233f1554da3Ssfking@fdwdc.com 234f1554da3Ssfking@fdwdc.com 235f1554da3Ssfking@fdwdc.com /* 236f1554da3Ssfking@fdwdc.com * Generic GPIO support 237f1554da3Ssfking@fdwdc.com */ 238f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL 239f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL 240f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL 241f1554da3Ssfking@fdwdc.com #define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL 242f1554da3Ssfking@fdwdc.com #define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL 243f1554da3Ssfking@fdwdc.com 244f1554da3Ssfking@fdwdc.com #define MCFGPIO_PIN_MAX 148 245f1554da3Ssfking@fdwdc.com #define MCFGPIO_IRQ_MAX 8 246f1554da3Ssfking@fdwdc.com #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 24791d60417SSteven King 24891d60417SSteven King #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E) 249f1554da3Ssfking@fdwdc.com #endif 250f1554da3Ssfking@fdwdc.com 251f1554da3Ssfking@fdwdc.com /* 252f317c71aSGreg Ungerer * PIT timer base addresses. 253f317c71aSGreg Ungerer */ 254f317c71aSGreg Ungerer #define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000) 255f317c71aSGreg Ungerer #define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000) 256f317c71aSGreg Ungerer #define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000) 257f317c71aSGreg Ungerer #define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000) 258f317c71aSGreg Ungerer 259f317c71aSGreg Ungerer /* 260f1554da3Ssfking@fdwdc.com * EPort 261f1554da3Ssfking@fdwdc.com */ 26257b48143SGreg Ungerer #define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) 263f1554da3Ssfking@fdwdc.com #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) 26457b48143SGreg Ungerer #define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) 265f1554da3Ssfking@fdwdc.com #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) 266f1554da3Ssfking@fdwdc.com #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) 26757b48143SGreg Ungerer #define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) 268f1554da3Ssfking@fdwdc.com 26949148020SSam Ravnborg /* 27049148020SSam Ravnborg * GPIO pins setups to enable the UARTs. 27149148020SSam Ravnborg */ 27249148020SSam Ravnborg #ifdef CONFIG_M5271 27349148020SSam Ravnborg #define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */ 27449148020SSam Ravnborg #define UART0_ENABLE_MASK 0x000f 27549148020SSam Ravnborg #define UART1_ENABLE_MASK 0x0ff0 27649148020SSam Ravnborg #define UART2_ENABLE_MASK 0x3000 27749148020SSam Ravnborg #endif 27849148020SSam Ravnborg #ifdef CONFIG_M5275 27949148020SSam Ravnborg #define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */ 28049148020SSam Ravnborg #define UART0_ENABLE_MASK 0x000f 28149148020SSam Ravnborg #define UART1_ENABLE_MASK 0x00f0 28249148020SSam Ravnborg #define UART2_ENABLE_MASK 0x3f00 28349148020SSam Ravnborg #endif 28449148020SSam Ravnborg 2854c0b008dSGreg Ungerer /* 2864c0b008dSGreg Ungerer * Reset Controll Unit (relative to IPSBAR). 2874c0b008dSGreg Ungerer */ 2884c0b008dSGreg Ungerer #define MCF_RCR 0x110000 2894c0b008dSGreg Ungerer #define MCF_RSR 0x110001 2904c0b008dSGreg Ungerer 2914c0b008dSGreg Ungerer #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 2924c0b008dSGreg Ungerer #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 2934c0b008dSGreg Ungerer 29449148020SSam Ravnborg /****************************************************************************/ 29549148020SSam Ravnborg #endif /* m527xsim_h */ 296