149148020SSam Ravnborg /****************************************************************************/ 249148020SSam Ravnborg 349148020SSam Ravnborg /* 449148020SSam Ravnborg * m527xsim.h -- ColdFire 5270/5271 System Integration Module support. 549148020SSam Ravnborg * 649148020SSam Ravnborg * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com) 749148020SSam Ravnborg */ 849148020SSam Ravnborg 949148020SSam Ravnborg /****************************************************************************/ 1049148020SSam Ravnborg #ifndef m527xsim_h 1149148020SSam Ravnborg #define m527xsim_h 1249148020SSam Ravnborg /****************************************************************************/ 1349148020SSam Ravnborg 147fc82b65SGreg Ungerer #define CPU_NAME "COLDFIRE(m527x)" 15733f31b7SGreg Ungerer #define CPU_INSTR_PER_JIFFY 3 167fc82b65SGreg Ungerer 1749148020SSam Ravnborg 1849148020SSam Ravnborg /* 1949148020SSam Ravnborg * Define the 5270/5271 SIM register set addresses. 2049148020SSam Ravnborg */ 2149148020SSam Ravnborg #define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ 2249148020SSam Ravnborg #define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */ 2349148020SSam Ravnborg #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 2449148020SSam Ravnborg #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 2549148020SSam Ravnborg #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 2649148020SSam Ravnborg #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 2749148020SSam Ravnborg #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 2849148020SSam Ravnborg #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 2949148020SSam Ravnborg #define MCFINTC_IRLR 0x18 /* */ 3049148020SSam Ravnborg #define MCFINTC_IACKL 0x19 /* */ 3149148020SSam Ravnborg #define MCFINTC_ICR0 0x40 /* Base ICR register */ 3249148020SSam Ravnborg 3349148020SSam Ravnborg #define MCFINT_VECBASE 64 /* Vector base number */ 3449148020SSam Ravnborg #define MCFINT_UART0 13 /* Interrupt number for UART0 */ 3549148020SSam Ravnborg #define MCFINT_UART1 14 /* Interrupt number for UART1 */ 3649148020SSam Ravnborg #define MCFINT_UART2 15 /* Interrupt number for UART2 */ 3791d60417SSteven King #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 3849148020SSam Ravnborg #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ 3949148020SSam Ravnborg 4049148020SSam Ravnborg /* 4149148020SSam Ravnborg * SDRAM configuration registers. 4249148020SSam Ravnborg */ 4349148020SSam Ravnborg #ifdef CONFIG_M5271 4449148020SSam Ravnborg #define MCFSIM_DCR 0x40 /* SDRAM control */ 4549148020SSam Ravnborg #define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ 4649148020SSam Ravnborg #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ 4749148020SSam Ravnborg #define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ 4849148020SSam Ravnborg #define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ 4949148020SSam Ravnborg #endif 5049148020SSam Ravnborg #ifdef CONFIG_M5275 5149148020SSam Ravnborg #define MCFSIM_DMR 0x40 /* SDRAM mode */ 5249148020SSam Ravnborg #define MCFSIM_DCR 0x44 /* SDRAM control */ 5349148020SSam Ravnborg #define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */ 5449148020SSam Ravnborg #define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */ 5549148020SSam Ravnborg #define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */ 5649148020SSam Ravnborg #define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */ 5749148020SSam Ravnborg #define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */ 5849148020SSam Ravnborg #define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ 5949148020SSam Ravnborg #endif 6049148020SSam Ravnborg 6157015421SGreg Ungerer /* 6257015421SGreg Ungerer * UART module. 6357015421SGreg Ungerer */ 6457015421SGreg Ungerer #define MCFUART_BASE1 0x200 /* Base address of UART1 */ 6557015421SGreg Ungerer #define MCFUART_BASE2 0x240 /* Base address of UART2 */ 6657015421SGreg Ungerer #define MCFUART_BASE3 0x280 /* Base address of UART3 */ 67f1554da3Ssfking@fdwdc.com 68f1554da3Ssfking@fdwdc.com #ifdef CONFIG_M5271 69f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) 70f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) 71f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) 72f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003) 73f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004) 74f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005) 75f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006) 76f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007) 77f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008) 78f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009) 79f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A) 80f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B) 81f1554da3Ssfking@fdwdc.com 82f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010) 83f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011) 84f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012) 85f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013) 86f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014) 87f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015) 88f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016) 89f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017) 90f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018) 91f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019) 92f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A) 93f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B) 94f1554da3Ssfking@fdwdc.com 95f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020) 96f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021) 97f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022) 98f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023) 99f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024) 100f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025) 101f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026) 102f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027) 103f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028) 104f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029) 105f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A) 106f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B) 107f1554da3Ssfking@fdwdc.com 108f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030) 109f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031) 110f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032) 111f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033) 112f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034) 113f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035) 114f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036) 115f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037) 116f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038) 117f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039) 118f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A) 119f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B) 120f1554da3Ssfking@fdwdc.com 121f1554da3Ssfking@fdwdc.com /* 122f1554da3Ssfking@fdwdc.com * Generic GPIO support 123f1554da3Ssfking@fdwdc.com */ 124f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR MCFGPIO_PODR_ADDR 125f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR 126f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR 127f1554da3Ssfking@fdwdc.com #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR 128f1554da3Ssfking@fdwdc.com #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR 129f1554da3Ssfking@fdwdc.com 130f1554da3Ssfking@fdwdc.com #define MCFGPIO_PIN_MAX 100 131f1554da3Ssfking@fdwdc.com #define MCFGPIO_IRQ_MAX 8 132f1554da3Ssfking@fdwdc.com #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 13391d60417SSteven King 13491d60417SSteven King #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) 13591d60417SSteven King #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) 136f1554da3Ssfking@fdwdc.com #endif 137f1554da3Ssfking@fdwdc.com 138f1554da3Ssfking@fdwdc.com #ifdef CONFIG_M5275 139f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004) 140f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100005) 141f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100008) 142f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FEC0H (MCF_IPSBAR + 0x10000A) 143f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FEC0L (MCF_IPSBAR + 0x10000B) 144f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x10000C) 145f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000D) 146f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x10000E) 147f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMERH (MCF_IPSBAR + 0x10000F) 148f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMERL (MCF_IPSBAR + 0x100010) 149f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100011) 150f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FEC1H (MCF_IPSBAR + 0x100012) 151f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FEC1L (MCF_IPSBAR + 0x100013) 152f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100014) 153f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_IRQ (MCF_IPSBAR + 0x100015) 154f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_USBH (MCF_IPSBAR + 0x100016) 155f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_USBL (MCF_IPSBAR + 0x100017) 156f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100018) 157f1554da3Ssfking@fdwdc.com 158f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100020) 159f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100021) 160f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100024) 161f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FEC0H (MCF_IPSBAR + 0x100026) 162f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FEC0L (MCF_IPSBAR + 0x100027) 163f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100028) 164f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x100029) 165f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x10002A) 166f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMERH (MCF_IPSBAR + 0x10002B) 167f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMERL (MCF_IPSBAR + 0x10002C) 168f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x10002D) 169f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FEC1H (MCF_IPSBAR + 0x10002E) 170f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FEC1L (MCF_IPSBAR + 0x10002F) 171f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100030) 172f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_IRQ (MCF_IPSBAR + 0x100031) 173f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_USBH (MCF_IPSBAR + 0x100032) 174f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_USBL (MCF_IPSBAR + 0x100033) 175f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100034) 176f1554da3Ssfking@fdwdc.com 177f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x10003C) 178f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x10003D) 179f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100040) 180f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FEC0H (MCF_IPSBAR + 0x100042) 181f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FEC0L (MCF_IPSBAR + 0x100043) 182f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100044) 183f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x100045) 184f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100046) 185f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_TIMERH (MCF_IPSBAR + 0x100047) 186f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_TIMERL (MCF_IPSBAR + 0x100048) 187f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100049) 188f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FEC1H (MCF_IPSBAR + 0x10004A) 189f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FEC1L (MCF_IPSBAR + 0x10004B) 190f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x10004C) 191f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_IRQ (MCF_IPSBAR + 0x10004D) 192f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_USBH (MCF_IPSBAR + 0x10004E) 193f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_USBL (MCF_IPSBAR + 0x10004F) 194f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100050) 195f1554da3Ssfking@fdwdc.com 196f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100058) 197f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100059) 198f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x10005C) 199f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FEC0H (MCF_IPSBAR + 0x10005E) 200f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FEC0L (MCF_IPSBAR + 0x10005F) 201f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100060) 202f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x100061) 203f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100062) 204f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMERH (MCF_IPSBAR + 0x100063) 205f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMERL (MCF_IPSBAR + 0x100064) 206f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100065) 207f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FEC1H (MCF_IPSBAR + 0x100066) 208f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FEC1L (MCF_IPSBAR + 0x100067) 209f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100068) 210f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_IRQ (MCF_IPSBAR + 0x100069) 211f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_USBH (MCF_IPSBAR + 0x10006A) 212f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_USBL (MCF_IPSBAR + 0x10006B) 213f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x10006C) 214f1554da3Ssfking@fdwdc.com 215f1554da3Ssfking@fdwdc.com 216f1554da3Ssfking@fdwdc.com /* 217f1554da3Ssfking@fdwdc.com * Generic GPIO support 218f1554da3Ssfking@fdwdc.com */ 219f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL 220f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL 221f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL 222f1554da3Ssfking@fdwdc.com #define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL 223f1554da3Ssfking@fdwdc.com #define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL 224f1554da3Ssfking@fdwdc.com 225f1554da3Ssfking@fdwdc.com #define MCFGPIO_PIN_MAX 148 226f1554da3Ssfking@fdwdc.com #define MCFGPIO_IRQ_MAX 8 227f1554da3Ssfking@fdwdc.com #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 22891d60417SSteven King 22991d60417SSteven King #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E) 230f1554da3Ssfking@fdwdc.com #endif 231f1554da3Ssfking@fdwdc.com 232f1554da3Ssfking@fdwdc.com /* 233f1554da3Ssfking@fdwdc.com * EPort 234f1554da3Ssfking@fdwdc.com */ 235f1554da3Ssfking@fdwdc.com 236f1554da3Ssfking@fdwdc.com #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) 237f1554da3Ssfking@fdwdc.com #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) 238f1554da3Ssfking@fdwdc.com #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) 239f1554da3Ssfking@fdwdc.com 240f1554da3Ssfking@fdwdc.com 24191d60417SSteven King 24249148020SSam Ravnborg /* 24349148020SSam Ravnborg * GPIO pins setups to enable the UARTs. 24449148020SSam Ravnborg */ 24549148020SSam Ravnborg #ifdef CONFIG_M5271 24649148020SSam Ravnborg #define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */ 24749148020SSam Ravnborg #define UART0_ENABLE_MASK 0x000f 24849148020SSam Ravnborg #define UART1_ENABLE_MASK 0x0ff0 24949148020SSam Ravnborg #define UART2_ENABLE_MASK 0x3000 25049148020SSam Ravnborg #endif 25149148020SSam Ravnborg #ifdef CONFIG_M5275 25249148020SSam Ravnborg #define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */ 25349148020SSam Ravnborg #define UART0_ENABLE_MASK 0x000f 25449148020SSam Ravnborg #define UART1_ENABLE_MASK 0x00f0 25549148020SSam Ravnborg #define UART2_ENABLE_MASK 0x3f00 25649148020SSam Ravnborg #endif 25749148020SSam Ravnborg 2584c0b008dSGreg Ungerer /* 2594c0b008dSGreg Ungerer * Reset Controll Unit (relative to IPSBAR). 2604c0b008dSGreg Ungerer */ 2614c0b008dSGreg Ungerer #define MCF_RCR 0x110000 2624c0b008dSGreg Ungerer #define MCF_RSR 0x110001 2634c0b008dSGreg Ungerer 2644c0b008dSGreg Ungerer #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 2654c0b008dSGreg Ungerer #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 2664c0b008dSGreg Ungerer 26749148020SSam Ravnborg /****************************************************************************/ 26849148020SSam Ravnborg #endif /* m527xsim_h */ 269