149148020SSam Ravnborg /****************************************************************************/ 249148020SSam Ravnborg 349148020SSam Ravnborg /* 449148020SSam Ravnborg * m527xsim.h -- ColdFire 5270/5271 System Integration Module support. 549148020SSam Ravnborg * 649148020SSam Ravnborg * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com) 749148020SSam Ravnborg */ 849148020SSam Ravnborg 949148020SSam Ravnborg /****************************************************************************/ 1049148020SSam Ravnborg #ifndef m527xsim_h 1149148020SSam Ravnborg #define m527xsim_h 1249148020SSam Ravnborg /****************************************************************************/ 1349148020SSam Ravnborg 147fc82b65SGreg Ungerer #define CPU_NAME "COLDFIRE(m527x)" 15733f31b7SGreg Ungerer #define CPU_INSTR_PER_JIFFY 3 16ce3de78aSGreg Ungerer #define MCF_BUSCLK (MCF_CLK / 2) 177fc82b65SGreg Ungerer 18a12cf0a8SGreg Ungerer #include <asm/m52xxacr.h> 1949148020SSam Ravnborg 2049148020SSam Ravnborg /* 2149148020SSam Ravnborg * Define the 5270/5271 SIM register set addresses. 2249148020SSam Ravnborg */ 23254eef74SGreg Ungerer #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ 24254eef74SGreg Ungerer #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */ 25254eef74SGreg Ungerer 2649148020SSam Ravnborg #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 2749148020SSam Ravnborg #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 2849148020SSam Ravnborg #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 2949148020SSam Ravnborg #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 3049148020SSam Ravnborg #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 3149148020SSam Ravnborg #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 3249148020SSam Ravnborg #define MCFINTC_IRLR 0x18 /* */ 3349148020SSam Ravnborg #define MCFINTC_IACKL 0x19 /* */ 3449148020SSam Ravnborg #define MCFINTC_ICR0 0x40 /* Base ICR register */ 3549148020SSam Ravnborg 3649148020SSam Ravnborg #define MCFINT_VECBASE 64 /* Vector base number */ 3749148020SSam Ravnborg #define MCFINT_UART0 13 /* Interrupt number for UART0 */ 3849148020SSam Ravnborg #define MCFINT_UART1 14 /* Interrupt number for UART1 */ 3949148020SSam Ravnborg #define MCFINT_UART2 15 /* Interrupt number for UART2 */ 4091d60417SSteven King #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 41308bfc12SGreg Ungerer #define MCFINT_FECRX0 23 /* Interrupt number for FEC0 */ 42308bfc12SGreg Ungerer #define MCFINT_FECTX0 27 /* Interrupt number for FEC0 */ 43308bfc12SGreg Ungerer #define MCFINT_FECENTC0 29 /* Interrupt number for FEC0 */ 4449148020SSam Ravnborg #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ 4549148020SSam Ravnborg 46308bfc12SGreg Ungerer #define MCFINT2_VECBASE 128 /* Vector base number 2 */ 47308bfc12SGreg Ungerer #define MCFINT2_FECRX1 23 /* Interrupt number for FEC1 */ 48308bfc12SGreg Ungerer #define MCFINT2_FECTX1 27 /* Interrupt number for FEC1 */ 49308bfc12SGreg Ungerer #define MCFINT2_FECENTC1 29 /* Interrupt number for FEC1 */ 50308bfc12SGreg Ungerer 5120e681fdSGreg Ungerer #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) 5220e681fdSGreg Ungerer #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) 5320e681fdSGreg Ungerer #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) 5420e681fdSGreg Ungerer 55308bfc12SGreg Ungerer #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) 56308bfc12SGreg Ungerer #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) 57308bfc12SGreg Ungerer #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 58308bfc12SGreg Ungerer #define MCF_IRQ_FECRX1 (MCFINT2_VECBASE + MCFINT2_FECRX1) 59308bfc12SGreg Ungerer #define MCF_IRQ_FECTX1 (MCFINT2_VECBASE + MCFINT2_FECTX1) 60308bfc12SGreg Ungerer #define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1) 61308bfc12SGreg Ungerer 6249148020SSam Ravnborg /* 6349148020SSam Ravnborg * SDRAM configuration registers. 6449148020SSam Ravnborg */ 6549148020SSam Ravnborg #ifdef CONFIG_M5271 666a92e198SGreg Ungerer #define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */ 676a92e198SGreg Ungerer #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ 686a92e198SGreg Ungerer #define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */ 696a92e198SGreg Ungerer #define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */ 706a92e198SGreg Ungerer #define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */ 7149148020SSam Ravnborg #endif 7249148020SSam Ravnborg #ifdef CONFIG_M5275 736a92e198SGreg Ungerer #define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */ 746a92e198SGreg Ungerer #define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */ 756a92e198SGreg Ungerer #define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */ 766a92e198SGreg Ungerer #define MCFSIM_DCFG2 (MCF_IPSBAR + 0x4c) /* Configuration 2 */ 776a92e198SGreg Ungerer #define MCFSIM_DBAR0 (MCF_IPSBAR + 0x50) /* Base address 0 */ 786a92e198SGreg Ungerer #define MCFSIM_DMR0 (MCF_IPSBAR + 0x54) /* Address mask 0 */ 796a92e198SGreg Ungerer #define MCFSIM_DBAR1 (MCF_IPSBAR + 0x58) /* Base address 1 */ 806a92e198SGreg Ungerer #define MCFSIM_DMR1 (MCF_IPSBAR + 0x5c) /* Address mask 1 */ 8149148020SSam Ravnborg #endif 8249148020SSam Ravnborg 8357015421SGreg Ungerer /* 84babc08b7SGreg Ungerer * DMA unit base addresses. 85babc08b7SGreg Ungerer */ 86babc08b7SGreg Ungerer #define MCFDMA_BASE0 (MCF_IPSBAR + 0x100) 87babc08b7SGreg Ungerer #define MCFDMA_BASE1 (MCF_IPSBAR + 0x140) 88babc08b7SGreg Ungerer #define MCFDMA_BASE2 (MCF_IPSBAR + 0x180) 89babc08b7SGreg Ungerer #define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0) 90babc08b7SGreg Ungerer 91babc08b7SGreg Ungerer /* 9257015421SGreg Ungerer * UART module. 9357015421SGreg Ungerer */ 9420e681fdSGreg Ungerer #define MCFUART_BASE0 (MCF_IPSBAR + 0x200) 9520e681fdSGreg Ungerer #define MCFUART_BASE1 (MCF_IPSBAR + 0x240) 9620e681fdSGreg Ungerer #define MCFUART_BASE2 (MCF_IPSBAR + 0x280) 979a6b0c73SGreg Ungerer 989a6b0c73SGreg Ungerer /* 999a6b0c73SGreg Ungerer * FEC ethernet module. 1009a6b0c73SGreg Ungerer */ 1019a6b0c73SGreg Ungerer #define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000) 1029a6b0c73SGreg Ungerer #define MCFFEC_SIZE0 0x800 1039a6b0c73SGreg Ungerer #define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800) 1049a6b0c73SGreg Ungerer #define MCFFEC_SIZE1 0x800 105f1554da3Ssfking@fdwdc.com 106f1554da3Ssfking@fdwdc.com #ifdef CONFIG_M5271 107f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) 108f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) 109f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) 110f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003) 111f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004) 112f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005) 113f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006) 114f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007) 115f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008) 116f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009) 117f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A) 118f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B) 119f1554da3Ssfking@fdwdc.com 120f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010) 121f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011) 122f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012) 123f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013) 124f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014) 125f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015) 126f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016) 127f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017) 128f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018) 129f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019) 130f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A) 131f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B) 132f1554da3Ssfking@fdwdc.com 133f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020) 134f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021) 135f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022) 136f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023) 137f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024) 138f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025) 139f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026) 140f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027) 141f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028) 142f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029) 143f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A) 144f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B) 145f1554da3Ssfking@fdwdc.com 146f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030) 147f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031) 148f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032) 149f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033) 150f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034) 151f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035) 152f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036) 153f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037) 154f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038) 155f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039) 156f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A) 157f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B) 158f1554da3Ssfking@fdwdc.com 159f1554da3Ssfking@fdwdc.com /* 160f1554da3Ssfking@fdwdc.com * Generic GPIO support 161f1554da3Ssfking@fdwdc.com */ 162f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR MCFGPIO_PODR_ADDR 163f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR 164f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR 165f1554da3Ssfking@fdwdc.com #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR 166f1554da3Ssfking@fdwdc.com #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR 167f1554da3Ssfking@fdwdc.com 168f1554da3Ssfking@fdwdc.com #define MCFGPIO_PIN_MAX 100 169f1554da3Ssfking@fdwdc.com #define MCFGPIO_IRQ_MAX 8 170f1554da3Ssfking@fdwdc.com #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 17191d60417SSteven King 17291d60417SSteven King #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) 17391d60417SSteven King #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) 174f1554da3Ssfking@fdwdc.com #endif 175f1554da3Ssfking@fdwdc.com 176f1554da3Ssfking@fdwdc.com #ifdef CONFIG_M5275 177f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004) 178f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100005) 179f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100008) 180f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FEC0H (MCF_IPSBAR + 0x10000A) 181f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FEC0L (MCF_IPSBAR + 0x10000B) 182f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x10000C) 183f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000D) 184f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x10000E) 185f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMERH (MCF_IPSBAR + 0x10000F) 186f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMERL (MCF_IPSBAR + 0x100010) 187f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100011) 188f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FEC1H (MCF_IPSBAR + 0x100012) 189f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FEC1L (MCF_IPSBAR + 0x100013) 190f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100014) 191f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_IRQ (MCF_IPSBAR + 0x100015) 192f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_USBH (MCF_IPSBAR + 0x100016) 193f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_USBL (MCF_IPSBAR + 0x100017) 194f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100018) 195f1554da3Ssfking@fdwdc.com 196f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100020) 197f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100021) 198f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100024) 199f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FEC0H (MCF_IPSBAR + 0x100026) 200f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FEC0L (MCF_IPSBAR + 0x100027) 201f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100028) 202f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x100029) 203f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x10002A) 204f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMERH (MCF_IPSBAR + 0x10002B) 205f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMERL (MCF_IPSBAR + 0x10002C) 206f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x10002D) 207f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FEC1H (MCF_IPSBAR + 0x10002E) 208f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FEC1L (MCF_IPSBAR + 0x10002F) 209f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100030) 210f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_IRQ (MCF_IPSBAR + 0x100031) 211f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_USBH (MCF_IPSBAR + 0x100032) 212f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_USBL (MCF_IPSBAR + 0x100033) 213f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100034) 214f1554da3Ssfking@fdwdc.com 215f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x10003C) 216f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x10003D) 217f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100040) 218f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FEC0H (MCF_IPSBAR + 0x100042) 219f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FEC0L (MCF_IPSBAR + 0x100043) 220f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100044) 221f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x100045) 222f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100046) 223f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_TIMERH (MCF_IPSBAR + 0x100047) 224f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_TIMERL (MCF_IPSBAR + 0x100048) 225f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100049) 226f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FEC1H (MCF_IPSBAR + 0x10004A) 227f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FEC1L (MCF_IPSBAR + 0x10004B) 228f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x10004C) 229f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_IRQ (MCF_IPSBAR + 0x10004D) 230f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_USBH (MCF_IPSBAR + 0x10004E) 231f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_USBL (MCF_IPSBAR + 0x10004F) 232f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100050) 233f1554da3Ssfking@fdwdc.com 234f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100058) 235f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100059) 236f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x10005C) 237f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FEC0H (MCF_IPSBAR + 0x10005E) 238f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FEC0L (MCF_IPSBAR + 0x10005F) 239f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100060) 240f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x100061) 241f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100062) 242f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMERH (MCF_IPSBAR + 0x100063) 243f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMERL (MCF_IPSBAR + 0x100064) 244f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100065) 245f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FEC1H (MCF_IPSBAR + 0x100066) 246f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FEC1L (MCF_IPSBAR + 0x100067) 247f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100068) 248f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_IRQ (MCF_IPSBAR + 0x100069) 249f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_USBH (MCF_IPSBAR + 0x10006A) 250f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_USBL (MCF_IPSBAR + 0x10006B) 251f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x10006C) 252f1554da3Ssfking@fdwdc.com 253f1554da3Ssfking@fdwdc.com 254f1554da3Ssfking@fdwdc.com /* 255f1554da3Ssfking@fdwdc.com * Generic GPIO support 256f1554da3Ssfking@fdwdc.com */ 257f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL 258f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL 259f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL 260f1554da3Ssfking@fdwdc.com #define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL 261f1554da3Ssfking@fdwdc.com #define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL 262f1554da3Ssfking@fdwdc.com 263f1554da3Ssfking@fdwdc.com #define MCFGPIO_PIN_MAX 148 264f1554da3Ssfking@fdwdc.com #define MCFGPIO_IRQ_MAX 8 265f1554da3Ssfking@fdwdc.com #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 26691d60417SSteven King 26791d60417SSteven King #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E) 268f1554da3Ssfking@fdwdc.com #endif 269f1554da3Ssfking@fdwdc.com 270f1554da3Ssfking@fdwdc.com /* 271f317c71aSGreg Ungerer * PIT timer base addresses. 272f317c71aSGreg Ungerer */ 273f317c71aSGreg Ungerer #define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000) 274f317c71aSGreg Ungerer #define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000) 275f317c71aSGreg Ungerer #define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000) 276f317c71aSGreg Ungerer #define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000) 277f317c71aSGreg Ungerer 278f317c71aSGreg Ungerer /* 279f1554da3Ssfking@fdwdc.com * EPort 280f1554da3Ssfking@fdwdc.com */ 28157b48143SGreg Ungerer #define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) 282f1554da3Ssfking@fdwdc.com #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) 28357b48143SGreg Ungerer #define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) 284f1554da3Ssfking@fdwdc.com #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) 285f1554da3Ssfking@fdwdc.com #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) 28657b48143SGreg Ungerer #define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) 287f1554da3Ssfking@fdwdc.com 28849148020SSam Ravnborg /* 28949148020SSam Ravnborg * GPIO pins setups to enable the UARTs. 29049148020SSam Ravnborg */ 29149148020SSam Ravnborg #ifdef CONFIG_M5271 29249148020SSam Ravnborg #define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */ 29349148020SSam Ravnborg #define UART0_ENABLE_MASK 0x000f 29449148020SSam Ravnborg #define UART1_ENABLE_MASK 0x0ff0 29549148020SSam Ravnborg #define UART2_ENABLE_MASK 0x3000 29649148020SSam Ravnborg #endif 29749148020SSam Ravnborg #ifdef CONFIG_M5275 29849148020SSam Ravnborg #define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */ 29949148020SSam Ravnborg #define UART0_ENABLE_MASK 0x000f 30049148020SSam Ravnborg #define UART1_ENABLE_MASK 0x00f0 30149148020SSam Ravnborg #define UART2_ENABLE_MASK 0x3f00 30249148020SSam Ravnborg #endif 30349148020SSam Ravnborg 3044c0b008dSGreg Ungerer /* 30525985edcSLucas De Marchi * Reset Control Unit (relative to IPSBAR). 3064c0b008dSGreg Ungerer */ 3074c0b008dSGreg Ungerer #define MCF_RCR 0x110000 3084c0b008dSGreg Ungerer #define MCF_RSR 0x110001 3094c0b008dSGreg Ungerer 3104c0b008dSGreg Ungerer #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 3114c0b008dSGreg Ungerer #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 3124c0b008dSGreg Ungerer 31349148020SSam Ravnborg /****************************************************************************/ 31449148020SSam Ravnborg #endif /* m527xsim_h */ 315