149148020SSam Ravnborg /****************************************************************************/ 249148020SSam Ravnborg 349148020SSam Ravnborg /* 449148020SSam Ravnborg * m527xsim.h -- ColdFire 5270/5271 System Integration Module support. 549148020SSam Ravnborg * 649148020SSam Ravnborg * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com) 749148020SSam Ravnborg */ 849148020SSam Ravnborg 949148020SSam Ravnborg /****************************************************************************/ 1049148020SSam Ravnborg #ifndef m527xsim_h 1149148020SSam Ravnborg #define m527xsim_h 1249148020SSam Ravnborg /****************************************************************************/ 1349148020SSam Ravnborg 147fc82b65SGreg Ungerer #define CPU_NAME "COLDFIRE(m527x)" 15733f31b7SGreg Ungerer #define CPU_INSTR_PER_JIFFY 3 16ce3de78aSGreg Ungerer #define MCF_BUSCLK (MCF_CLK / 2) 177fc82b65SGreg Ungerer 18a12cf0a8SGreg Ungerer #include <asm/m52xxacr.h> 1949148020SSam Ravnborg 2049148020SSam Ravnborg /* 2149148020SSam Ravnborg * Define the 5270/5271 SIM register set addresses. 2249148020SSam Ravnborg */ 23254eef74SGreg Ungerer #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ 24254eef74SGreg Ungerer #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */ 25254eef74SGreg Ungerer 2649148020SSam Ravnborg #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 2749148020SSam Ravnborg #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 2849148020SSam Ravnborg #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 2949148020SSam Ravnborg #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 3049148020SSam Ravnborg #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 3149148020SSam Ravnborg #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 3249148020SSam Ravnborg #define MCFINTC_IRLR 0x18 /* */ 3349148020SSam Ravnborg #define MCFINTC_IACKL 0x19 /* */ 3449148020SSam Ravnborg #define MCFINTC_ICR0 0x40 /* Base ICR register */ 3549148020SSam Ravnborg 3649148020SSam Ravnborg #define MCFINT_VECBASE 64 /* Vector base number */ 3749148020SSam Ravnborg #define MCFINT_UART0 13 /* Interrupt number for UART0 */ 3849148020SSam Ravnborg #define MCFINT_UART1 14 /* Interrupt number for UART1 */ 3949148020SSam Ravnborg #define MCFINT_UART2 15 /* Interrupt number for UART2 */ 4091d60417SSteven King #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 4149148020SSam Ravnborg #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ 4249148020SSam Ravnborg 4320e681fdSGreg Ungerer #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) 4420e681fdSGreg Ungerer #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) 4520e681fdSGreg Ungerer #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) 4620e681fdSGreg Ungerer 4749148020SSam Ravnborg /* 4849148020SSam Ravnborg * SDRAM configuration registers. 4949148020SSam Ravnborg */ 5049148020SSam Ravnborg #ifdef CONFIG_M5271 516a92e198SGreg Ungerer #define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */ 526a92e198SGreg Ungerer #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ 536a92e198SGreg Ungerer #define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */ 546a92e198SGreg Ungerer #define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */ 556a92e198SGreg Ungerer #define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */ 5649148020SSam Ravnborg #endif 5749148020SSam Ravnborg #ifdef CONFIG_M5275 586a92e198SGreg Ungerer #define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */ 596a92e198SGreg Ungerer #define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */ 606a92e198SGreg Ungerer #define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */ 616a92e198SGreg Ungerer #define MCFSIM_DCFG2 (MCF_IPSBAR + 0x4c) /* Configuration 2 */ 626a92e198SGreg Ungerer #define MCFSIM_DBAR0 (MCF_IPSBAR + 0x50) /* Base address 0 */ 636a92e198SGreg Ungerer #define MCFSIM_DMR0 (MCF_IPSBAR + 0x54) /* Address mask 0 */ 646a92e198SGreg Ungerer #define MCFSIM_DBAR1 (MCF_IPSBAR + 0x58) /* Base address 1 */ 656a92e198SGreg Ungerer #define MCFSIM_DMR1 (MCF_IPSBAR + 0x5c) /* Address mask 1 */ 6649148020SSam Ravnborg #endif 6749148020SSam Ravnborg 6857015421SGreg Ungerer /* 69babc08b7SGreg Ungerer * DMA unit base addresses. 70babc08b7SGreg Ungerer */ 71babc08b7SGreg Ungerer #define MCFDMA_BASE0 (MCF_IPSBAR + 0x100) 72babc08b7SGreg Ungerer #define MCFDMA_BASE1 (MCF_IPSBAR + 0x140) 73babc08b7SGreg Ungerer #define MCFDMA_BASE2 (MCF_IPSBAR + 0x180) 74babc08b7SGreg Ungerer #define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0) 75babc08b7SGreg Ungerer 76babc08b7SGreg Ungerer /* 7757015421SGreg Ungerer * UART module. 7857015421SGreg Ungerer */ 7920e681fdSGreg Ungerer #define MCFUART_BASE0 (MCF_IPSBAR + 0x200) 8020e681fdSGreg Ungerer #define MCFUART_BASE1 (MCF_IPSBAR + 0x240) 8120e681fdSGreg Ungerer #define MCFUART_BASE2 (MCF_IPSBAR + 0x280) 829a6b0c73SGreg Ungerer 839a6b0c73SGreg Ungerer /* 849a6b0c73SGreg Ungerer * FEC ethernet module. 859a6b0c73SGreg Ungerer */ 869a6b0c73SGreg Ungerer #define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000) 879a6b0c73SGreg Ungerer #define MCFFEC_SIZE0 0x800 889a6b0c73SGreg Ungerer #define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800) 899a6b0c73SGreg Ungerer #define MCFFEC_SIZE1 0x800 90f1554da3Ssfking@fdwdc.com 91f1554da3Ssfking@fdwdc.com #ifdef CONFIG_M5271 92f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) 93f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) 94f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) 95f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003) 96f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004) 97f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005) 98f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006) 99f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007) 100f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008) 101f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009) 102f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A) 103f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B) 104f1554da3Ssfking@fdwdc.com 105f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010) 106f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011) 107f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012) 108f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013) 109f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014) 110f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015) 111f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016) 112f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017) 113f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018) 114f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019) 115f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A) 116f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B) 117f1554da3Ssfking@fdwdc.com 118f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020) 119f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021) 120f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022) 121f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023) 122f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024) 123f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025) 124f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026) 125f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027) 126f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028) 127f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029) 128f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A) 129f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B) 130f1554da3Ssfking@fdwdc.com 131f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030) 132f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031) 133f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032) 134f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033) 135f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034) 136f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035) 137f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036) 138f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037) 139f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038) 140f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039) 141f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A) 142f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B) 143f1554da3Ssfking@fdwdc.com 144f1554da3Ssfking@fdwdc.com /* 145f1554da3Ssfking@fdwdc.com * Generic GPIO support 146f1554da3Ssfking@fdwdc.com */ 147f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR MCFGPIO_PODR_ADDR 148f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR 149f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR 150f1554da3Ssfking@fdwdc.com #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR 151f1554da3Ssfking@fdwdc.com #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR 152f1554da3Ssfking@fdwdc.com 153f1554da3Ssfking@fdwdc.com #define MCFGPIO_PIN_MAX 100 154f1554da3Ssfking@fdwdc.com #define MCFGPIO_IRQ_MAX 8 155f1554da3Ssfking@fdwdc.com #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 15691d60417SSteven King 15791d60417SSteven King #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) 15891d60417SSteven King #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) 159f1554da3Ssfking@fdwdc.com #endif 160f1554da3Ssfking@fdwdc.com 161f1554da3Ssfking@fdwdc.com #ifdef CONFIG_M5275 162f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004) 163f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100005) 164f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100008) 165f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FEC0H (MCF_IPSBAR + 0x10000A) 166f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FEC0L (MCF_IPSBAR + 0x10000B) 167f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x10000C) 168f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000D) 169f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x10000E) 170f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMERH (MCF_IPSBAR + 0x10000F) 171f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMERL (MCF_IPSBAR + 0x100010) 172f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100011) 173f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FEC1H (MCF_IPSBAR + 0x100012) 174f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FEC1L (MCF_IPSBAR + 0x100013) 175f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100014) 176f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_IRQ (MCF_IPSBAR + 0x100015) 177f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_USBH (MCF_IPSBAR + 0x100016) 178f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_USBL (MCF_IPSBAR + 0x100017) 179f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100018) 180f1554da3Ssfking@fdwdc.com 181f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100020) 182f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100021) 183f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100024) 184f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FEC0H (MCF_IPSBAR + 0x100026) 185f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FEC0L (MCF_IPSBAR + 0x100027) 186f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100028) 187f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x100029) 188f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x10002A) 189f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMERH (MCF_IPSBAR + 0x10002B) 190f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMERL (MCF_IPSBAR + 0x10002C) 191f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x10002D) 192f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FEC1H (MCF_IPSBAR + 0x10002E) 193f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FEC1L (MCF_IPSBAR + 0x10002F) 194f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100030) 195f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_IRQ (MCF_IPSBAR + 0x100031) 196f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_USBH (MCF_IPSBAR + 0x100032) 197f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_USBL (MCF_IPSBAR + 0x100033) 198f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100034) 199f1554da3Ssfking@fdwdc.com 200f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x10003C) 201f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x10003D) 202f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100040) 203f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FEC0H (MCF_IPSBAR + 0x100042) 204f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FEC0L (MCF_IPSBAR + 0x100043) 205f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100044) 206f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x100045) 207f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100046) 208f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_TIMERH (MCF_IPSBAR + 0x100047) 209f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_TIMERL (MCF_IPSBAR + 0x100048) 210f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100049) 211f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FEC1H (MCF_IPSBAR + 0x10004A) 212f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FEC1L (MCF_IPSBAR + 0x10004B) 213f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x10004C) 214f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_IRQ (MCF_IPSBAR + 0x10004D) 215f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_USBH (MCF_IPSBAR + 0x10004E) 216f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_USBL (MCF_IPSBAR + 0x10004F) 217f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100050) 218f1554da3Ssfking@fdwdc.com 219f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100058) 220f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100059) 221f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x10005C) 222f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FEC0H (MCF_IPSBAR + 0x10005E) 223f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FEC0L (MCF_IPSBAR + 0x10005F) 224f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100060) 225f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x100061) 226f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100062) 227f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMERH (MCF_IPSBAR + 0x100063) 228f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMERL (MCF_IPSBAR + 0x100064) 229f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100065) 230f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FEC1H (MCF_IPSBAR + 0x100066) 231f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FEC1L (MCF_IPSBAR + 0x100067) 232f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100068) 233f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_IRQ (MCF_IPSBAR + 0x100069) 234f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_USBH (MCF_IPSBAR + 0x10006A) 235f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_USBL (MCF_IPSBAR + 0x10006B) 236f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x10006C) 237f1554da3Ssfking@fdwdc.com 238f1554da3Ssfking@fdwdc.com 239f1554da3Ssfking@fdwdc.com /* 240f1554da3Ssfking@fdwdc.com * Generic GPIO support 241f1554da3Ssfking@fdwdc.com */ 242f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL 243f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL 244f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL 245f1554da3Ssfking@fdwdc.com #define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL 246f1554da3Ssfking@fdwdc.com #define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL 247f1554da3Ssfking@fdwdc.com 248f1554da3Ssfking@fdwdc.com #define MCFGPIO_PIN_MAX 148 249f1554da3Ssfking@fdwdc.com #define MCFGPIO_IRQ_MAX 8 250f1554da3Ssfking@fdwdc.com #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 25191d60417SSteven King 25291d60417SSteven King #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E) 253f1554da3Ssfking@fdwdc.com #endif 254f1554da3Ssfking@fdwdc.com 255f1554da3Ssfking@fdwdc.com /* 256f317c71aSGreg Ungerer * PIT timer base addresses. 257f317c71aSGreg Ungerer */ 258f317c71aSGreg Ungerer #define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000) 259f317c71aSGreg Ungerer #define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000) 260f317c71aSGreg Ungerer #define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000) 261f317c71aSGreg Ungerer #define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000) 262f317c71aSGreg Ungerer 263f317c71aSGreg Ungerer /* 264f1554da3Ssfking@fdwdc.com * EPort 265f1554da3Ssfking@fdwdc.com */ 26657b48143SGreg Ungerer #define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) 267f1554da3Ssfking@fdwdc.com #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) 26857b48143SGreg Ungerer #define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) 269f1554da3Ssfking@fdwdc.com #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) 270f1554da3Ssfking@fdwdc.com #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) 27157b48143SGreg Ungerer #define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) 272f1554da3Ssfking@fdwdc.com 27349148020SSam Ravnborg /* 27449148020SSam Ravnborg * GPIO pins setups to enable the UARTs. 27549148020SSam Ravnborg */ 27649148020SSam Ravnborg #ifdef CONFIG_M5271 27749148020SSam Ravnborg #define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */ 27849148020SSam Ravnborg #define UART0_ENABLE_MASK 0x000f 27949148020SSam Ravnborg #define UART1_ENABLE_MASK 0x0ff0 28049148020SSam Ravnborg #define UART2_ENABLE_MASK 0x3000 28149148020SSam Ravnborg #endif 28249148020SSam Ravnborg #ifdef CONFIG_M5275 28349148020SSam Ravnborg #define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */ 28449148020SSam Ravnborg #define UART0_ENABLE_MASK 0x000f 28549148020SSam Ravnborg #define UART1_ENABLE_MASK 0x00f0 28649148020SSam Ravnborg #define UART2_ENABLE_MASK 0x3f00 28749148020SSam Ravnborg #endif 28849148020SSam Ravnborg 2894c0b008dSGreg Ungerer /* 29025985edcSLucas De Marchi * Reset Control Unit (relative to IPSBAR). 2914c0b008dSGreg Ungerer */ 2924c0b008dSGreg Ungerer #define MCF_RCR 0x110000 2934c0b008dSGreg Ungerer #define MCF_RSR 0x110001 2944c0b008dSGreg Ungerer 2954c0b008dSGreg Ungerer #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 2964c0b008dSGreg Ungerer #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 2974c0b008dSGreg Ungerer 29849148020SSam Ravnborg /****************************************************************************/ 29949148020SSam Ravnborg #endif /* m527xsim_h */ 300