149148020SSam Ravnborg /****************************************************************************/ 249148020SSam Ravnborg 349148020SSam Ravnborg /* 449148020SSam Ravnborg * m5272sim.h -- ColdFire 5272 System Integration Module support. 549148020SSam Ravnborg * 649148020SSam Ravnborg * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) 749148020SSam Ravnborg * (C) Copyright 2000, Lineo Inc. (www.lineo.com) 849148020SSam Ravnborg */ 949148020SSam Ravnborg 1049148020SSam Ravnborg /****************************************************************************/ 1149148020SSam Ravnborg #ifndef m5272sim_h 1249148020SSam Ravnborg #define m5272sim_h 1349148020SSam Ravnborg /****************************************************************************/ 1449148020SSam Ravnborg 157fc82b65SGreg Ungerer #define CPU_NAME "COLDFIRE(m5272)" 16733f31b7SGreg Ungerer #define CPU_INSTR_PER_JIFFY 3 17ce3de78aSGreg Ungerer #define MCF_BUSCLK MCF_CLK 187fc82b65SGreg Ungerer 19a12cf0a8SGreg Ungerer #include <asm/m52xxacr.h> 20a12cf0a8SGreg Ungerer 2149148020SSam Ravnborg /* 2249148020SSam Ravnborg * Define the 5272 SIM register set addresses. 2349148020SSam Ravnborg */ 2449148020SSam Ravnborg #define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */ 2549148020SSam Ravnborg #define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/ 2649148020SSam Ravnborg #define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */ 2749148020SSam Ravnborg #define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */ 2849148020SSam Ravnborg #define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */ 2949148020SSam Ravnborg 3049148020SSam Ravnborg #define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */ 3149148020SSam Ravnborg #define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */ 3249148020SSam Ravnborg #define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */ 3349148020SSam Ravnborg #define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */ 3449148020SSam Ravnborg 3549148020SSam Ravnborg #define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */ 3649148020SSam Ravnborg #define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */ 3749148020SSam Ravnborg #define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */ 3849148020SSam Ravnborg #define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */ 3949148020SSam Ravnborg 4049148020SSam Ravnborg #define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */ 4149148020SSam Ravnborg #define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */ 4249148020SSam Ravnborg #define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */ 4349148020SSam Ravnborg #define MCFSIM_WER 0x28c /* Watchdog event (r/w) */ 4449148020SSam Ravnborg 4549148020SSam Ravnborg #define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */ 4649148020SSam Ravnborg #define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */ 4749148020SSam Ravnborg #define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */ 4849148020SSam Ravnborg #define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */ 4949148020SSam Ravnborg #define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */ 5049148020SSam Ravnborg #define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */ 5149148020SSam Ravnborg #define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */ 5249148020SSam Ravnborg #define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */ 5349148020SSam Ravnborg #define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */ 5449148020SSam Ravnborg #define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */ 5549148020SSam Ravnborg #define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */ 5649148020SSam Ravnborg #define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */ 5749148020SSam Ravnborg #define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */ 5849148020SSam Ravnborg #define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */ 5949148020SSam Ravnborg #define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */ 6049148020SSam Ravnborg #define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */ 6149148020SSam Ravnborg 6249148020SSam Ravnborg #define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */ 6349148020SSam Ravnborg #define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */ 6449148020SSam Ravnborg #define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */ 6549148020SSam Ravnborg #define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */ 6649148020SSam Ravnborg #define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */ 6749148020SSam Ravnborg #define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */ 6849148020SSam Ravnborg #define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ 6949148020SSam Ravnborg #define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ 7049148020SSam Ravnborg 7157015421SGreg Ungerer #define MCFUART_BASE1 0x100 /* Base address of UART1 */ 7257015421SGreg Ungerer #define MCFUART_BASE2 0x140 /* Base address of UART2 */ 7357015421SGreg Ungerer 74316f2c48Ssfking@fdwdc.com #define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */ 75316f2c48Ssfking@fdwdc.com #define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */ 76316f2c48Ssfking@fdwdc.com #define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */ 77316f2c48Ssfking@fdwdc.com #define MCFSIM_PBCNT (MCF_MBAR + 0x88) /* Port B Control (r/w) */ 78316f2c48Ssfking@fdwdc.com #define MCFSIM_PBDDR (MCF_MBAR + 0x8c) /* Port B Direction (r/w) */ 79316f2c48Ssfking@fdwdc.com #define MCFSIM_PBDAT (MCF_MBAR + 0x8e) /* Port B Data (r/w) */ 80316f2c48Ssfking@fdwdc.com #define MCFSIM_PCDDR (MCF_MBAR + 0x94) /* Port C Direction (r/w) */ 81316f2c48Ssfking@fdwdc.com #define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */ 82316f2c48Ssfking@fdwdc.com #define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */ 8349148020SSam Ravnborg 84babc08b7SGreg Ungerer #define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */ 85babc08b7SGreg Ungerer 8658f0ac98SGreg Ungerer #define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */ 8758f0ac98SGreg Ungerer #define MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */ 8858f0ac98SGreg Ungerer #define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */ 8958f0ac98SGreg Ungerer #define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */ 9058f0ac98SGreg Ungerer 9104b75b10SGreg Ungerer /* 9204b75b10SGreg Ungerer * Define system peripheral IRQ usage. 9304b75b10SGreg Ungerer */ 949075216dSGreg Ungerer #define MCFINT_VECBASE 64 /* Base of interrupts */ 959075216dSGreg Ungerer #define MCF_IRQ_SPURIOUS 64 /* User Spurious */ 969075216dSGreg Ungerer #define MCF_IRQ_EINT1 65 /* External Interrupt 1 */ 979075216dSGreg Ungerer #define MCF_IRQ_EINT2 66 /* External Interrupt 2 */ 989075216dSGreg Ungerer #define MCF_IRQ_EINT3 67 /* External Interrupt 3 */ 999075216dSGreg Ungerer #define MCF_IRQ_EINT4 68 /* External Interrupt 4 */ 1009075216dSGreg Ungerer #define MCF_IRQ_TIMER1 69 /* Timer 1 */ 1019075216dSGreg Ungerer #define MCF_IRQ_TIMER2 70 /* Timer 2 */ 1029075216dSGreg Ungerer #define MCF_IRQ_TIMER3 71 /* Timer 3 */ 1039075216dSGreg Ungerer #define MCF_IRQ_TIMER4 72 /* Timer 4 */ 1049075216dSGreg Ungerer #define MCF_IRQ_UART1 73 /* UART 1 */ 1059075216dSGreg Ungerer #define MCF_IRQ_UART2 74 /* UART 2 */ 1069075216dSGreg Ungerer #define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */ 1079075216dSGreg Ungerer #define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */ 1089075216dSGreg Ungerer #define MCF_IRQ_USB0 77 /* USB Endpoint 0 */ 1099075216dSGreg Ungerer #define MCF_IRQ_USB1 78 /* USB Endpoint 1 */ 1109075216dSGreg Ungerer #define MCF_IRQ_USB2 79 /* USB Endpoint 2 */ 1119075216dSGreg Ungerer #define MCF_IRQ_USB3 80 /* USB Endpoint 3 */ 1129075216dSGreg Ungerer #define MCF_IRQ_USB4 81 /* USB Endpoint 4 */ 1139075216dSGreg Ungerer #define MCF_IRQ_USB5 82 /* USB Endpoint 5 */ 1149075216dSGreg Ungerer #define MCF_IRQ_USB6 83 /* USB Endpoint 6 */ 1159075216dSGreg Ungerer #define MCF_IRQ_USB7 84 /* USB Endpoint 7 */ 1169075216dSGreg Ungerer #define MCF_IRQ_DMA 85 /* DMA Controller */ 1179075216dSGreg Ungerer #define MCF_IRQ_ERX 86 /* Ethernet Receiver */ 1189075216dSGreg Ungerer #define MCF_IRQ_ETX 87 /* Ethernet Transmitter */ 1199075216dSGreg Ungerer #define MCF_IRQ_ENTC 88 /* Ethernet Non-Time Critical */ 1209075216dSGreg Ungerer #define MCF_IRQ_QSPI 89 /* Queued Serial Interface */ 1219075216dSGreg Ungerer #define MCF_IRQ_EINT5 90 /* External Interrupt 5 */ 1229075216dSGreg Ungerer #define MCF_IRQ_EINT6 91 /* External Interrupt 6 */ 1239075216dSGreg Ungerer #define MCF_IRQ_SWTO 92 /* Software Watchdog */ 1249075216dSGreg Ungerer #define MCFINT_VECMAX 95 /* Maxmum interrupt */ 1259075216dSGreg Ungerer 1269075216dSGreg Ungerer #define MCF_IRQ_TIMER MCF_IRQ_TIMER1 1279075216dSGreg Ungerer #define MCF_IRQ_PROFILER MCF_IRQ_TIMER2 12849148020SSam Ravnborg 129316f2c48Ssfking@fdwdc.com /* 130316f2c48Ssfking@fdwdc.com * Generic GPIO support 131316f2c48Ssfking@fdwdc.com */ 132316f2c48Ssfking@fdwdc.com #define MCFGPIO_PIN_MAX 48 133316f2c48Ssfking@fdwdc.com #define MCFGPIO_IRQ_MAX -1 134316f2c48Ssfking@fdwdc.com #define MCFGPIO_IRQ_VECBASE -1 13549148020SSam Ravnborg /****************************************************************************/ 13649148020SSam Ravnborg #endif /* m5272sim_h */ 137