104e037aaSSteven King /****************************************************************************/ 204e037aaSSteven King 304e037aaSSteven King /* 404e037aaSSteven King * m525xsim.h -- ColdFire 525x System Integration Module support. 504e037aaSSteven King * 604e037aaSSteven King * (C) Copyright 2012, Steven king <sfking@fdwdc.com> 704e037aaSSteven King * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com) 804e037aaSSteven King */ 904e037aaSSteven King 1004e037aaSSteven King /****************************************************************************/ 1104e037aaSSteven King #ifndef m525xsim_h 1204e037aaSSteven King #define m525xsim_h 1304e037aaSSteven King /****************************************************************************/ 1404e037aaSSteven King 1504e037aaSSteven King #define CPU_NAME "COLDFIRE(m525x)" 1604e037aaSSteven King #define CPU_INSTR_PER_JIFFY 3 1704e037aaSSteven King #define MCF_BUSCLK (MCF_CLK / 2) 1804e037aaSSteven King 1904e037aaSSteven King #include <asm/m52xxacr.h> 2004e037aaSSteven King 2104e037aaSSteven King /* 2204e037aaSSteven King * The 525x has a second MBAR region, define its address. 2304e037aaSSteven King */ 2404e037aaSSteven King #define MCF_MBAR2 0x80000000 2504e037aaSSteven King 2604e037aaSSteven King /* 2704e037aaSSteven King * Define the 525x SIM register set addresses. 2804e037aaSSteven King */ 29e1e362dcSGreg Ungerer #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */ 30e1e362dcSGreg Ungerer #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ 3104e037aaSSteven King #define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ 3204e037aaSSteven King #define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ 3304e037aaSSteven King #define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ 346a3a786dSGreg Ungerer #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */ 356a3a786dSGreg Ungerer #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */ 3604e037aaSSteven King #define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ 3704e037aaSSteven King #define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ 3804e037aaSSteven King #define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ 3904e037aaSSteven King #define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ 4004e037aaSSteven King #define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ 4104e037aaSSteven King #define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ 4204e037aaSSteven King #define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ 4304e037aaSSteven King #define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ 4404e037aaSSteven King #define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ 4504e037aaSSteven King #define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ 4604e037aaSSteven King #define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ 4704e037aaSSteven King #define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ 4804e037aaSSteven King 4904e037aaSSteven King #define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ 5004e037aaSSteven King #define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ 5104e037aaSSteven King #define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ 5204e037aaSSteven King #define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ 5304e037aaSSteven King #define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ 5404e037aaSSteven King #define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ 5504e037aaSSteven King #define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ 5604e037aaSSteven King #define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ 5704e037aaSSteven King #define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ 5804e037aaSSteven King #define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ 5904e037aaSSteven King #define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ 6004e037aaSSteven King #define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ 6104e037aaSSteven King #define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */ 6204e037aaSSteven King #define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ 6304e037aaSSteven King #define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ 6404e037aaSSteven King 6504e037aaSSteven King #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ 6604e037aaSSteven King #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ 6704e037aaSSteven King #define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */ 6804e037aaSSteven King 6904e037aaSSteven King /* 7004e037aaSSteven King * Secondary Interrupt Controller (in MBAR2) 7104e037aaSSteven King */ 7204e037aaSSteven King #define MCFINTC2_INTBASE (MCF_MBAR2 + 0x168) /* Base Vector Reg */ 7304e037aaSSteven King #define MCFINTC2_INTPRI1 (MCF_MBAR2 + 0x140) /* 0-7 priority */ 7404e037aaSSteven King #define MCFINTC2_INTPRI2 (MCF_MBAR2 + 0x144) /* 8-15 priority */ 7504e037aaSSteven King #define MCFINTC2_INTPRI3 (MCF_MBAR2 + 0x148) /* 16-23 priority */ 7604e037aaSSteven King #define MCFINTC2_INTPRI4 (MCF_MBAR2 + 0x14c) /* 24-31 priority */ 7704e037aaSSteven King #define MCFINTC2_INTPRI5 (MCF_MBAR2 + 0x150) /* 32-39 priority */ 7804e037aaSSteven King #define MCFINTC2_INTPRI6 (MCF_MBAR2 + 0x154) /* 40-47 priority */ 7904e037aaSSteven King #define MCFINTC2_INTPRI7 (MCF_MBAR2 + 0x158) /* 48-55 priority */ 8004e037aaSSteven King #define MCFINTC2_INTPRI8 (MCF_MBAR2 + 0x15c) /* 56-63 priority */ 8104e037aaSSteven King 8204e037aaSSteven King #define MCFINTC2_INTPRI_REG(i) (MCFINTC2_INTPRI1 + \ 8304e037aaSSteven King ((((i) - MCFINTC2_VECBASE) / 8) * 4)) 8404e037aaSSteven King #define MCFINTC2_INTPRI_BITS(b, i) ((b) << (((i) % 8) * 4)) 8504e037aaSSteven King 8604e037aaSSteven King /* 8704e037aaSSteven King * Timer module. 8804e037aaSSteven King */ 8904e037aaSSteven King #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ 9004e037aaSSteven King #define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ 9104e037aaSSteven King 9204e037aaSSteven King /* 9304e037aaSSteven King * UART module. 9404e037aaSSteven King */ 9504e037aaSSteven King #define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */ 9604e037aaSSteven King #define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */ 9704e037aaSSteven King 9804e037aaSSteven King /* 9904e037aaSSteven King * QSPI module. 10004e037aaSSteven King */ 10104e037aaSSteven King #define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */ 10204e037aaSSteven King #define MCFQSPI_SIZE 0x40 /* Register set size */ 10304e037aaSSteven King 10404e037aaSSteven King 10504e037aaSSteven King #define MCFQSPI_CS0 15 10604e037aaSSteven King #define MCFQSPI_CS1 16 10704e037aaSSteven King #define MCFQSPI_CS2 24 10804e037aaSSteven King #define MCFQSPI_CS3 28 10904e037aaSSteven King 11004e037aaSSteven King /* 11104e037aaSSteven King * I2C module. 11204e037aaSSteven King */ 11304e037aaSSteven King #define MCFI2C_BASE0 (MCF_MBAR + 0x280) /* Base addreess I2C0 */ 11404e037aaSSteven King #define MCFI2C_SIZE0 0x20 /* Register set size */ 11504e037aaSSteven King 11604e037aaSSteven King #define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base addreess I2C1 */ 11704e037aaSSteven King #define MCFI2C_SIZE1 0x20 /* Register set size */ 11804e037aaSSteven King /* 11904e037aaSSteven King * DMA unit base addresses. 12004e037aaSSteven King */ 12104e037aaSSteven King #define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ 12204e037aaSSteven King #define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ 12304e037aaSSteven King #define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ 12404e037aaSSteven King #define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ 12504e037aaSSteven King 12604e037aaSSteven King /* 12704e037aaSSteven King * Some symbol defines for the above... 12804e037aaSSteven King */ 12904e037aaSSteven King #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ 13004e037aaSSteven King #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ 13104e037aaSSteven King #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ 13204e037aaSSteven King #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */ 13304e037aaSSteven King #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ 13404e037aaSSteven King #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ 13504e037aaSSteven King #define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ 13604e037aaSSteven King #define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ 13704e037aaSSteven King #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ 13804e037aaSSteven King #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 13904e037aaSSteven King #define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */ 14004e037aaSSteven King 14104e037aaSSteven King /* 14204e037aaSSteven King * Define system peripheral IRQ usage. 14304e037aaSSteven King */ 14404e037aaSSteven King #define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */ 14504e037aaSSteven King #define MCF_IRQ_I2C0 29 14604e037aaSSteven King #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 14704e037aaSSteven King #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 14804e037aaSSteven King 14904e037aaSSteven King #define MCF_IRQ_UART0 73 /* UART0 */ 15004e037aaSSteven King #define MCF_IRQ_UART1 74 /* UART1 */ 15104e037aaSSteven King 15204e037aaSSteven King /* 15304e037aaSSteven King * Define the base interrupt for the second interrupt controller. 15404e037aaSSteven King * We set it to 128, out of the way of the base interrupts, and plenty 15504e037aaSSteven King * of room for its 64 interrupts. 15604e037aaSSteven King */ 15704e037aaSSteven King #define MCFINTC2_VECBASE 128 15804e037aaSSteven King 15904e037aaSSteven King #define MCF_IRQ_GPIO0 (MCFINTC2_VECBASE + 32) 16004e037aaSSteven King #define MCF_IRQ_GPIO1 (MCFINTC2_VECBASE + 33) 16104e037aaSSteven King #define MCF_IRQ_GPIO2 (MCFINTC2_VECBASE + 34) 16204e037aaSSteven King #define MCF_IRQ_GPIO3 (MCFINTC2_VECBASE + 35) 16304e037aaSSteven King #define MCF_IRQ_GPIO4 (MCFINTC2_VECBASE + 36) 16404e037aaSSteven King #define MCF_IRQ_GPIO5 (MCFINTC2_VECBASE + 37) 16504e037aaSSteven King #define MCF_IRQ_GPIO6 (MCFINTC2_VECBASE + 38) 16604e037aaSSteven King 16704e037aaSSteven King #define MCF_IRQ_USBWUP (MCFINTC2_VECBASE + 40) 16804e037aaSSteven King #define MCF_IRQ_I2C1 (MCFINTC2_VECBASE + 62) 16904e037aaSSteven King 17004e037aaSSteven King /* 17104e037aaSSteven King * General purpose IO registers (in MBAR2). 17204e037aaSSteven King */ 17304e037aaSSteven King #define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */ 17404e037aaSSteven King #define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */ 17504e037aaSSteven King #define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */ 17604e037aaSSteven King #define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */ 17704e037aaSSteven King #define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */ 17804e037aaSSteven King #define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */ 17904e037aaSSteven King #define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */ 18004e037aaSSteven King #define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */ 18104e037aaSSteven King 18204e037aaSSteven King #define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */ 18304e037aaSSteven King #define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */ 18404e037aaSSteven King #define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */ 18504e037aaSSteven King 18604e037aaSSteven King /* 18704e037aaSSteven King * Generic GPIO support 18804e037aaSSteven King */ 18904e037aaSSteven King #define MCFGPIO_PIN_MAX 64 19004e037aaSSteven King #define MCFGPIO_IRQ_MAX 7 19104e037aaSSteven King #define MCFGPIO_IRQ_VECBASE MCF_IRQ_GPIO0 19204e037aaSSteven King 19304e037aaSSteven King /****************************************************************************/ 19404e037aaSSteven King #endif /* m525xsim_h */ 195