104e037aaSSteven King /****************************************************************************/ 204e037aaSSteven King 304e037aaSSteven King /* 404e037aaSSteven King * m525xsim.h -- ColdFire 525x System Integration Module support. 504e037aaSSteven King * 604e037aaSSteven King * (C) Copyright 2012, Steven king <sfking@fdwdc.com> 704e037aaSSteven King * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com) 804e037aaSSteven King */ 904e037aaSSteven King 1004e037aaSSteven King /****************************************************************************/ 1104e037aaSSteven King #ifndef m525xsim_h 1204e037aaSSteven King #define m525xsim_h 1304e037aaSSteven King /****************************************************************************/ 1404e037aaSSteven King 155a4acf3eSGreg Ungerer /* 165a4acf3eSGreg Ungerer * This header supports ColdFire 5249, 5251 and 5253. There are a few 175a4acf3eSGreg Ungerer * little differences between them, but most of the peripheral support 185a4acf3eSGreg Ungerer * can be used by all of them. 195a4acf3eSGreg Ungerer */ 2004e037aaSSteven King #define CPU_NAME "COLDFIRE(m525x)" 2104e037aaSSteven King #define CPU_INSTR_PER_JIFFY 3 2204e037aaSSteven King #define MCF_BUSCLK (MCF_CLK / 2) 2304e037aaSSteven King 2404e037aaSSteven King #include <asm/m52xxacr.h> 2504e037aaSSteven King 2604e037aaSSteven King /* 2704e037aaSSteven King * The 525x has a second MBAR region, define its address. 2804e037aaSSteven King */ 2904e037aaSSteven King #define MCF_MBAR2 0x80000000 3004e037aaSSteven King 3104e037aaSSteven King /* 3204e037aaSSteven King * Define the 525x SIM register set addresses. 3304e037aaSSteven King */ 34e1e362dcSGreg Ungerer #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */ 35e1e362dcSGreg Ungerer #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ 36660b73e3SGreg Ungerer #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ 37660b73e3SGreg Ungerer #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */ 3835142b91SGreg Ungerer #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */ 396a3a786dSGreg Ungerer #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */ 406a3a786dSGreg Ungerer #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */ 41c986a3d5SGreg Ungerer #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */ 42c986a3d5SGreg Ungerer #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */ 43c986a3d5SGreg Ungerer #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */ 44c986a3d5SGreg Ungerer #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */ 45c986a3d5SGreg Ungerer #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */ 46c986a3d5SGreg Ungerer #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */ 47c986a3d5SGreg Ungerer #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */ 48c986a3d5SGreg Ungerer #define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */ 49c986a3d5SGreg Ungerer #define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */ 50c986a3d5SGreg Ungerer #define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */ 51c986a3d5SGreg Ungerer #define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */ 52c986a3d5SGreg Ungerer #define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */ 5304e037aaSSteven King 541419ea3bSGreg Ungerer #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */ 551419ea3bSGreg Ungerer #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */ 561419ea3bSGreg Ungerer #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */ 571419ea3bSGreg Ungerer #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */ 581419ea3bSGreg Ungerer #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */ 591419ea3bSGreg Ungerer #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */ 601419ea3bSGreg Ungerer #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */ 611419ea3bSGreg Ungerer #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */ 621419ea3bSGreg Ungerer #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ 631419ea3bSGreg Ungerer #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */ 641419ea3bSGreg Ungerer #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */ 651419ea3bSGreg Ungerer #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ 661419ea3bSGreg Ungerer #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */ 671419ea3bSGreg Ungerer #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */ 681419ea3bSGreg Ungerer #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */ 6904e037aaSSteven King 7004e037aaSSteven King #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ 7104e037aaSSteven King #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ 7204e037aaSSteven King #define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */ 735a4acf3eSGreg Ungerer #define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */ 745a4acf3eSGreg Ungerer #define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */ 7504e037aaSSteven King 7604e037aaSSteven King /* 7704e037aaSSteven King * Secondary Interrupt Controller (in MBAR2) 7804e037aaSSteven King */ 7904e037aaSSteven King #define MCFINTC2_INTBASE (MCF_MBAR2 + 0x168) /* Base Vector Reg */ 8004e037aaSSteven King #define MCFINTC2_INTPRI1 (MCF_MBAR2 + 0x140) /* 0-7 priority */ 8104e037aaSSteven King #define MCFINTC2_INTPRI2 (MCF_MBAR2 + 0x144) /* 8-15 priority */ 8204e037aaSSteven King #define MCFINTC2_INTPRI3 (MCF_MBAR2 + 0x148) /* 16-23 priority */ 8304e037aaSSteven King #define MCFINTC2_INTPRI4 (MCF_MBAR2 + 0x14c) /* 24-31 priority */ 8404e037aaSSteven King #define MCFINTC2_INTPRI5 (MCF_MBAR2 + 0x150) /* 32-39 priority */ 8504e037aaSSteven King #define MCFINTC2_INTPRI6 (MCF_MBAR2 + 0x154) /* 40-47 priority */ 8604e037aaSSteven King #define MCFINTC2_INTPRI7 (MCF_MBAR2 + 0x158) /* 48-55 priority */ 8704e037aaSSteven King #define MCFINTC2_INTPRI8 (MCF_MBAR2 + 0x15c) /* 56-63 priority */ 8804e037aaSSteven King 8904e037aaSSteven King #define MCFINTC2_INTPRI_REG(i) (MCFINTC2_INTPRI1 + \ 9004e037aaSSteven King ((((i) - MCFINTC2_VECBASE) / 8) * 4)) 9104e037aaSSteven King #define MCFINTC2_INTPRI_BITS(b, i) ((b) << (((i) % 8) * 4)) 9204e037aaSSteven King 9304e037aaSSteven King /* 9404e037aaSSteven King * Timer module. 9504e037aaSSteven King */ 9604e037aaSSteven King #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ 9704e037aaSSteven King #define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ 9804e037aaSSteven King 9904e037aaSSteven King /* 10004e037aaSSteven King * UART module. 10104e037aaSSteven King */ 10204e037aaSSteven King #define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */ 10304e037aaSSteven King #define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */ 10404e037aaSSteven King 10504e037aaSSteven King /* 10604e037aaSSteven King * QSPI module. 10704e037aaSSteven King */ 108e93e91f2SSteven King #define MCFQSPI_BASE (MCF_MBAR + 0x400) /* Base address QSPI */ 10904e037aaSSteven King #define MCFQSPI_SIZE 0x40 /* Register set size */ 11004e037aaSSteven King 1115a4acf3eSGreg Ungerer #ifdef CONFIG_M5249 1125a4acf3eSGreg Ungerer #define MCFQSPI_CS0 29 1135a4acf3eSGreg Ungerer #define MCFQSPI_CS1 24 1145a4acf3eSGreg Ungerer #define MCFQSPI_CS2 21 1155a4acf3eSGreg Ungerer #define MCFQSPI_CS3 22 1165a4acf3eSGreg Ungerer #else 11704e037aaSSteven King #define MCFQSPI_CS0 15 11804e037aaSSteven King #define MCFQSPI_CS1 16 11904e037aaSSteven King #define MCFQSPI_CS2 24 12004e037aaSSteven King #define MCFQSPI_CS3 28 1215a4acf3eSGreg Ungerer #endif 12204e037aaSSteven King 12304e037aaSSteven King /* 12404e037aaSSteven King * I2C module. 12504e037aaSSteven King */ 12686a8280aSAndrea Gelmini #define MCFI2C_BASE0 (MCF_MBAR + 0x280) /* Base address I2C0 */ 12704e037aaSSteven King #define MCFI2C_SIZE0 0x20 /* Register set size */ 12804e037aaSSteven King 12986a8280aSAndrea Gelmini #define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base address I2C1 */ 13004e037aaSSteven King #define MCFI2C_SIZE1 0x20 /* Register set size */ 1315a4acf3eSGreg Ungerer 13204e037aaSSteven King /* 13304e037aaSSteven King * DMA unit base addresses. 13404e037aaSSteven King */ 13504e037aaSSteven King #define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ 13604e037aaSSteven King #define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ 13704e037aaSSteven King #define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ 13804e037aaSSteven King #define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ 13904e037aaSSteven King 14004e037aaSSteven King /* 14104e037aaSSteven King * Some symbol defines for the above... 14204e037aaSSteven King */ 14304e037aaSSteven King #define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ 14404e037aaSSteven King #define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ 14504e037aaSSteven King #define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ 14604e037aaSSteven King #define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */ 14704e037aaSSteven King #define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ 14804e037aaSSteven King #define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ 14904e037aaSSteven King #define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ 15004e037aaSSteven King #define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ 15104e037aaSSteven King #define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ 15204e037aaSSteven King #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 15304e037aaSSteven King #define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */ 15404e037aaSSteven King 15504e037aaSSteven King /* 15604e037aaSSteven King * Define system peripheral IRQ usage. 15704e037aaSSteven King */ 15804e037aaSSteven King #define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */ 15904e037aaSSteven King #define MCF_IRQ_I2C0 29 16004e037aaSSteven King #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 16104e037aaSSteven King #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 16204e037aaSSteven King 16304e037aaSSteven King #define MCF_IRQ_UART0 73 /* UART0 */ 16404e037aaSSteven King #define MCF_IRQ_UART1 74 /* UART1 */ 16504e037aaSSteven King 16604e037aaSSteven King /* 16704e037aaSSteven King * Define the base interrupt for the second interrupt controller. 16804e037aaSSteven King * We set it to 128, out of the way of the base interrupts, and plenty 16904e037aaSSteven King * of room for its 64 interrupts. 17004e037aaSSteven King */ 17104e037aaSSteven King #define MCFINTC2_VECBASE 128 17204e037aaSSteven King 17304e037aaSSteven King #define MCF_IRQ_GPIO0 (MCFINTC2_VECBASE + 32) 17404e037aaSSteven King #define MCF_IRQ_GPIO1 (MCFINTC2_VECBASE + 33) 17504e037aaSSteven King #define MCF_IRQ_GPIO2 (MCFINTC2_VECBASE + 34) 17604e037aaSSteven King #define MCF_IRQ_GPIO3 (MCFINTC2_VECBASE + 35) 17704e037aaSSteven King #define MCF_IRQ_GPIO4 (MCFINTC2_VECBASE + 36) 17804e037aaSSteven King #define MCF_IRQ_GPIO5 (MCFINTC2_VECBASE + 37) 17904e037aaSSteven King #define MCF_IRQ_GPIO6 (MCFINTC2_VECBASE + 38) 1805a4acf3eSGreg Ungerer #define MCF_IRQ_GPIO7 (MCFINTC2_VECBASE + 39) 18104e037aaSSteven King 18204e037aaSSteven King #define MCF_IRQ_USBWUP (MCFINTC2_VECBASE + 40) 18304e037aaSSteven King #define MCF_IRQ_I2C1 (MCFINTC2_VECBASE + 62) 18404e037aaSSteven King 18504e037aaSSteven King /* 18604e037aaSSteven King * General purpose IO registers (in MBAR2). 18704e037aaSSteven King */ 18804e037aaSSteven King #define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */ 18904e037aaSSteven King #define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */ 19004e037aaSSteven King #define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */ 19104e037aaSSteven King #define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */ 19204e037aaSSteven King #define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */ 19304e037aaSSteven King #define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */ 19404e037aaSSteven King #define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */ 19504e037aaSSteven King #define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */ 19604e037aaSSteven King 19704e037aaSSteven King #define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */ 19804e037aaSSteven King #define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */ 19904e037aaSSteven King #define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */ 20004e037aaSSteven King 2015a4acf3eSGreg Ungerer #define MCFSIM2_DMAROUTE (MCF_MBAR2 + 0x188) /* DMA routing */ 2025a4acf3eSGreg Ungerer #define MCFSIM2_IDECONFIG1 (MCF_MBAR2 + 0x18c) /* IDEconfig1 */ 2035a4acf3eSGreg Ungerer #define MCFSIM2_IDECONFIG2 (MCF_MBAR2 + 0x190) /* IDEconfig2 */ 2045a4acf3eSGreg Ungerer 20504e037aaSSteven King /* 20604e037aaSSteven King * Generic GPIO support 20704e037aaSSteven King */ 20804e037aaSSteven King #define MCFGPIO_PIN_MAX 64 2095a4acf3eSGreg Ungerer #ifdef CONFIG_M5249 2105a4acf3eSGreg Ungerer #define MCFGPIO_IRQ_MAX -1 2115a4acf3eSGreg Ungerer #define MCFGPIO_IRQ_VECBASE -1 2125a4acf3eSGreg Ungerer #else 21304e037aaSSteven King #define MCFGPIO_IRQ_MAX 7 21404e037aaSSteven King #define MCFGPIO_IRQ_VECBASE MCF_IRQ_GPIO0 2155a4acf3eSGreg Ungerer #endif 21604e037aaSSteven King 21704e037aaSSteven King /****************************************************************************/ 2185a4acf3eSGreg Ungerer 2195a4acf3eSGreg Ungerer #ifdef __ASSEMBLER__ 2205a4acf3eSGreg Ungerer #ifdef CONFIG_M5249C3 2215a4acf3eSGreg Ungerer /* 2225a4acf3eSGreg Ungerer * The M5249C3 board needs a little help getting all its SIM devices 2235a4acf3eSGreg Ungerer * initialized at kernel start time. dBUG doesn't set much up, so 2245a4acf3eSGreg Ungerer * we need to do it manually. 2255a4acf3eSGreg Ungerer */ 2265a4acf3eSGreg Ungerer .macro m5249c3_setup 2275a4acf3eSGreg Ungerer /* 2285a4acf3eSGreg Ungerer * Set MBAR1 and MBAR2, just incase they are not set. 2295a4acf3eSGreg Ungerer */ 2305a4acf3eSGreg Ungerer movel #0x10000001,%a0 2315a4acf3eSGreg Ungerer movec %a0,%MBAR /* map MBAR region */ 2325a4acf3eSGreg Ungerer subql #1,%a0 /* get MBAR address in a0 */ 2335a4acf3eSGreg Ungerer 2345a4acf3eSGreg Ungerer movel #0x80000001,%a1 2355a4acf3eSGreg Ungerer movec %a1,#3086 /* map MBAR2 region */ 2365a4acf3eSGreg Ungerer subql #1,%a1 /* get MBAR2 address in a1 */ 2375a4acf3eSGreg Ungerer 2385a4acf3eSGreg Ungerer /* 2395a4acf3eSGreg Ungerer * Move secondary interrupts to their base (128). 2405a4acf3eSGreg Ungerer */ 2415a4acf3eSGreg Ungerer moveb #MCFINTC2_VECBASE,%d0 2425a4acf3eSGreg Ungerer moveb %d0,0x16b(%a1) /* interrupt base register */ 2435a4acf3eSGreg Ungerer 2445a4acf3eSGreg Ungerer /* 2455a4acf3eSGreg Ungerer * Work around broken CSMR0/DRAM vector problem. 2465a4acf3eSGreg Ungerer */ 2475a4acf3eSGreg Ungerer movel #0x001F0021,%d0 /* disable C/I bit */ 2485a4acf3eSGreg Ungerer movel %d0,0x84(%a0) /* set CSMR0 */ 2495a4acf3eSGreg Ungerer 2505a4acf3eSGreg Ungerer /* 2515a4acf3eSGreg Ungerer * Disable the PLL firstly. (Who knows what state it is 2525a4acf3eSGreg Ungerer * in here!). 2535a4acf3eSGreg Ungerer */ 2545a4acf3eSGreg Ungerer movel 0x180(%a1),%d0 /* get current PLL value */ 2555a4acf3eSGreg Ungerer andl #0xfffffffe,%d0 /* PLL bypass first */ 2565a4acf3eSGreg Ungerer movel %d0,0x180(%a1) /* set PLL register */ 2575a4acf3eSGreg Ungerer nop 2585a4acf3eSGreg Ungerer 2595a4acf3eSGreg Ungerer #if CONFIG_CLOCK_FREQ == 140000000 2605a4acf3eSGreg Ungerer /* 2615a4acf3eSGreg Ungerer * Set initial clock frequency. This assumes M5249C3 board 2625a4acf3eSGreg Ungerer * is fitted with 11.2896MHz crystal. It will program the 2635a4acf3eSGreg Ungerer * PLL for 140MHz. Lets go fast :-) 2645a4acf3eSGreg Ungerer */ 2655a4acf3eSGreg Ungerer movel #0x125a40f0,%d0 /* set for 140MHz */ 2665a4acf3eSGreg Ungerer movel %d0,0x180(%a1) /* set PLL register */ 2675a4acf3eSGreg Ungerer orl #0x1,%d0 2685a4acf3eSGreg Ungerer movel %d0,0x180(%a1) /* set PLL register */ 2695a4acf3eSGreg Ungerer #endif 2705a4acf3eSGreg Ungerer 2715a4acf3eSGreg Ungerer /* 2725a4acf3eSGreg Ungerer * Setup CS1 for ethernet controller. 2735a4acf3eSGreg Ungerer * (Setup as per M5249C3 doco). 2745a4acf3eSGreg Ungerer */ 2755a4acf3eSGreg Ungerer movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */ 2765a4acf3eSGreg Ungerer movel %d0,0x8c(%a0) 2775a4acf3eSGreg Ungerer movel #0x001f0021,%d0 /* CS1 size of 1Mb */ 2785a4acf3eSGreg Ungerer movel %d0,0x90(%a0) 2795a4acf3eSGreg Ungerer movew #0x0080,%d0 /* CS1 = 16bit port, AA */ 2805a4acf3eSGreg Ungerer movew %d0,0x96(%a0) 2815a4acf3eSGreg Ungerer 2825a4acf3eSGreg Ungerer /* 2835a4acf3eSGreg Ungerer * Setup CS2 for IDE interface. 2845a4acf3eSGreg Ungerer */ 2855a4acf3eSGreg Ungerer movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */ 2865a4acf3eSGreg Ungerer movel %d0,0x98(%a0) 2875a4acf3eSGreg Ungerer movel #0x001f0001,%d0 /* CS2 size of 1MB */ 2885a4acf3eSGreg Ungerer movel %d0,0x9c(%a0) 2895a4acf3eSGreg Ungerer movew #0x0080,%d0 /* CS2 = 16bit, TA */ 2905a4acf3eSGreg Ungerer movew %d0,0xa2(%a0) 2915a4acf3eSGreg Ungerer 2925a4acf3eSGreg Ungerer movel #0x00107000,%d0 /* IDEconfig1 */ 2935a4acf3eSGreg Ungerer movel %d0,0x18c(%a1) 2945a4acf3eSGreg Ungerer movel #0x000c0400,%d0 /* IDEconfig2 */ 2955a4acf3eSGreg Ungerer movel %d0,0x190(%a1) 2965a4acf3eSGreg Ungerer 2975a4acf3eSGreg Ungerer movel #0x00080000,%d0 /* GPIO19, IDE reset bit */ 2985a4acf3eSGreg Ungerer orl %d0,0xc(%a1) /* function GPIO19 */ 2995a4acf3eSGreg Ungerer orl %d0,0x8(%a1) /* enable GPIO19 as output */ 3005a4acf3eSGreg Ungerer orl %d0,0x4(%a1) /* de-assert IDE reset */ 3015a4acf3eSGreg Ungerer .endm 3025a4acf3eSGreg Ungerer 3035a4acf3eSGreg Ungerer #define PLATFORM_SETUP m5249c3_setup 3045a4acf3eSGreg Ungerer 3055a4acf3eSGreg Ungerer #endif /* CONFIG_M5249C3 */ 3065a4acf3eSGreg Ungerer #endif /* __ASSEMBLER__ */ 3075a4acf3eSGreg Ungerer /****************************************************************************/ 30804e037aaSSteven King #endif /* m525xsim_h */ 309