1 /****************************************************************************/ 2 3 /* 4 * m520xsim.h -- ColdFire 5207/5208 System Integration Module support. 5 * 6 * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com) 7 */ 8 9 /****************************************************************************/ 10 #ifndef m520xsim_h 11 #define m520xsim_h 12 /****************************************************************************/ 13 14 #define CPU_NAME "COLDFIRE(m520x)" 15 #define CPU_INSTR_PER_JIFFY 3 16 17 #include <asm/m52xxacr.h> 18 19 /* 20 * Define the 520x SIM register set addresses. 21 */ 22 #define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */ 23 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 24 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 25 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 26 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 27 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 28 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 29 #define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */ 30 #define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */ 31 #define MCFINTC_ICR0 0x40 /* Base ICR register */ 32 33 /* 34 * The common interrupt controller code just wants to know the absolute 35 * address to the SIMR and CIMR registers (not offsets into IPSBAR). 36 * The 520x family only has a single INTC unit. 37 */ 38 #define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR) 39 #define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR) 40 #define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0) 41 #define MCFINTC1_SIMR (0) 42 #define MCFINTC1_CIMR (0) 43 #define MCFINTC1_ICR0 (0) 44 45 #define MCFINT_VECBASE 64 46 #define MCFINT_UART0 26 /* Interrupt number for UART0 */ 47 #define MCFINT_UART1 27 /* Interrupt number for UART1 */ 48 #define MCFINT_UART2 28 /* Interrupt number for UART2 */ 49 #define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 50 #define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ 51 52 /* 53 * SDRAM configuration registers. 54 */ 55 #define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */ 56 #define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */ 57 #define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */ 58 #define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */ 59 #define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */ 60 #define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */ 61 62 /* 63 * EPORT and GPIO registers. 64 */ 65 #define MCFEPORT_EPDDR 0xFC088002 66 #define MCFEPORT_EPDR 0xFC088004 67 #define MCFEPORT_EPPDR 0xFC088005 68 69 #define MCFGPIO_PODR_BUSCTL 0xFC0A4000 70 #define MCFGPIO_PODR_BE 0xFC0A4001 71 #define MCFGPIO_PODR_CS 0xFC0A4002 72 #define MCFGPIO_PODR_FECI2C 0xFC0A4003 73 #define MCFGPIO_PODR_QSPI 0xFC0A4004 74 #define MCFGPIO_PODR_TIMER 0xFC0A4005 75 #define MCFGPIO_PODR_UART 0xFC0A4006 76 #define MCFGPIO_PODR_FECH 0xFC0A4007 77 #define MCFGPIO_PODR_FECL 0xFC0A4008 78 79 #define MCFGPIO_PDDR_BUSCTL 0xFC0A400C 80 #define MCFGPIO_PDDR_BE 0xFC0A400D 81 #define MCFGPIO_PDDR_CS 0xFC0A400E 82 #define MCFGPIO_PDDR_FECI2C 0xFC0A400F 83 #define MCFGPIO_PDDR_QSPI 0xFC0A4010 84 #define MCFGPIO_PDDR_TIMER 0xFC0A4011 85 #define MCFGPIO_PDDR_UART 0xFC0A4012 86 #define MCFGPIO_PDDR_FECH 0xFC0A4013 87 #define MCFGPIO_PDDR_FECL 0xFC0A4014 88 89 #define MCFGPIO_PPDSDR_BUSCTL 0xFC0A401A 90 #define MCFGPIO_PPDSDR_BE 0xFC0A401B 91 #define MCFGPIO_PPDSDR_CS 0xFC0A401C 92 #define MCFGPIO_PPDSDR_FECI2C 0xFC0A401D 93 #define MCFGPIO_PPDSDR_QSPI 0xFC0A401E 94 #define MCFGPIO_PPDSDR_TIMER 0xFC0A401F 95 #define MCFGPIO_PPDSDR_UART 0xFC0A4021 96 #define MCFGPIO_PPDSDR_FECH 0xFC0A4021 97 #define MCFGPIO_PPDSDR_FECL 0xFC0A4022 98 99 #define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024 100 #define MCFGPIO_PCLRR_BE 0xFC0A4025 101 #define MCFGPIO_PCLRR_CS 0xFC0A4026 102 #define MCFGPIO_PCLRR_FECI2C 0xFC0A4027 103 #define MCFGPIO_PCLRR_QSPI 0xFC0A4028 104 #define MCFGPIO_PCLRR_TIMER 0xFC0A4029 105 #define MCFGPIO_PCLRR_UART 0xFC0A402A 106 #define MCFGPIO_PCLRR_FECH 0xFC0A402B 107 #define MCFGPIO_PCLRR_FECL 0xFC0A402C 108 109 /* 110 * Generic GPIO support 111 */ 112 #define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL 113 #define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL 114 #define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL 115 #define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL 116 #define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL 117 118 #define MCFGPIO_PIN_MAX 80 119 #define MCFGPIO_IRQ_MAX 8 120 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 121 122 #define MCF_GPIO_PAR_UART 0xFC0A4036 123 #define MCF_GPIO_PAR_FECI2C 0xFC0A4033 124 #define MCF_GPIO_PAR_QSPI 0xFC0A4034 125 #define MCF_GPIO_PAR_FEC 0xFC0A4038 126 127 #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) 128 #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) 129 130 #define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040) 131 #define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080) 132 133 #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) 134 #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) 135 136 /* 137 * PIT timer module. 138 */ 139 #define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */ 140 #define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */ 141 142 /* 143 * UART module. 144 */ 145 #define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */ 146 #define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */ 147 #define MCFUART_BASE3 0xFC068000 /* Base address of UART2 */ 148 149 /* 150 * FEC module. 151 */ 152 #define MCFFEC_BASE 0xFC030000 /* Base of FEC ethernet */ 153 #define MCFFEC_SIZE 0x800 /* Register set size */ 154 155 /* 156 * Reset Controll Unit. 157 */ 158 #define MCF_RCR 0xFC0A0000 159 #define MCF_RSR 0xFC0A0001 160 161 #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 162 #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 163 164 /****************************************************************************/ 165 #endif /* m520xsim_h */ 166