1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************/ 3 4 /* 5 * m520xsim.h -- ColdFire 5207/5208 System Integration Module support. 6 * 7 * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com) 8 */ 9 10 /****************************************************************************/ 11 #ifndef m520xsim_h 12 #define m520xsim_h 13 /****************************************************************************/ 14 15 #define CPU_NAME "COLDFIRE(m520x)" 16 #define CPU_INSTR_PER_JIFFY 3 17 #define MCF_BUSCLK (MCF_CLK / 2) 18 19 #include <asm/m52xxacr.h> 20 21 /* 22 * Define the 520x SIM register set addresses. 23 */ 24 #define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */ 25 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 26 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 27 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 28 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 29 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 30 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 31 #define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */ 32 #define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */ 33 #define MCFINTC_ICR0 0x40 /* Base ICR register */ 34 35 /* 36 * The common interrupt controller code just wants to know the absolute 37 * address to the SIMR and CIMR registers (not offsets into IPSBAR). 38 * The 520x family only has a single INTC unit. 39 */ 40 #define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR) 41 #define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR) 42 #define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0) 43 #define MCFINTC1_SIMR (0) 44 #define MCFINTC1_CIMR (0) 45 #define MCFINTC1_ICR0 (0) 46 #define MCFINTC2_SIMR (0) 47 #define MCFINTC2_CIMR (0) 48 #define MCFINTC2_ICR0 (0) 49 50 #define MCFINT_VECBASE 64 51 #define MCFINT_UART0 26 /* Interrupt number for UART0 */ 52 #define MCFINT_UART1 27 /* Interrupt number for UART1 */ 53 #define MCFINT_UART2 28 /* Interrupt number for UART2 */ 54 #define MCFINT_I2C0 30 /* Interrupt number for I2C */ 55 #define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 56 #define MCFINT_FECRX0 36 /* Interrupt number for FEC RX */ 57 #define MCFINT_FECTX0 40 /* Interrupt number for FEC RX */ 58 #define MCFINT_FECENTC0 42 /* Interrupt number for FEC RX */ 59 #define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ 60 61 #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) 62 #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) 63 #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) 64 65 #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) 66 #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) 67 #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 68 69 #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 70 #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) 71 72 #define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0) 73 /* 74 * SDRAM configuration registers. 75 */ 76 #define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */ 77 #define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */ 78 #define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */ 79 #define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */ 80 #define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */ 81 #define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */ 82 83 /* 84 * EPORT and GPIO registers. 85 */ 86 #define MCFEPORT_EPPAR 0xFC088000 87 #define MCFEPORT_EPDDR 0xFC088002 88 #define MCFEPORT_EPIER 0xFC088003 89 #define MCFEPORT_EPDR 0xFC088004 90 #define MCFEPORT_EPPDR 0xFC088005 91 #define MCFEPORT_EPFR 0xFC088006 92 93 #define MCFGPIO_PODR_BUSCTL 0xFC0A4000 94 #define MCFGPIO_PODR_BE 0xFC0A4001 95 #define MCFGPIO_PODR_CS 0xFC0A4002 96 #define MCFGPIO_PODR_FECI2C 0xFC0A4003 97 #define MCFGPIO_PODR_QSPI 0xFC0A4004 98 #define MCFGPIO_PODR_TIMER 0xFC0A4005 99 #define MCFGPIO_PODR_UART 0xFC0A4006 100 #define MCFGPIO_PODR_FECH 0xFC0A4007 101 #define MCFGPIO_PODR_FECL 0xFC0A4008 102 103 #define MCFGPIO_PDDR_BUSCTL 0xFC0A400C 104 #define MCFGPIO_PDDR_BE 0xFC0A400D 105 #define MCFGPIO_PDDR_CS 0xFC0A400E 106 #define MCFGPIO_PDDR_FECI2C 0xFC0A400F 107 #define MCFGPIO_PDDR_QSPI 0xFC0A4010 108 #define MCFGPIO_PDDR_TIMER 0xFC0A4011 109 #define MCFGPIO_PDDR_UART 0xFC0A4012 110 #define MCFGPIO_PDDR_FECH 0xFC0A4013 111 #define MCFGPIO_PDDR_FECL 0xFC0A4014 112 113 #define MCFGPIO_PPDSDR_CS 0xFC0A401A 114 #define MCFGPIO_PPDSDR_FECI2C 0xFC0A401B 115 #define MCFGPIO_PPDSDR_QSPI 0xFC0A401C 116 #define MCFGPIO_PPDSDR_TIMER 0xFC0A401D 117 #define MCFGPIO_PPDSDR_UART 0xFC0A401E 118 #define MCFGPIO_PPDSDR_FECH 0xFC0A401F 119 #define MCFGPIO_PPDSDR_FECL 0xFC0A4020 120 121 #define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024 122 #define MCFGPIO_PCLRR_BE 0xFC0A4025 123 #define MCFGPIO_PCLRR_CS 0xFC0A4026 124 #define MCFGPIO_PCLRR_FECI2C 0xFC0A4027 125 #define MCFGPIO_PCLRR_QSPI 0xFC0A4028 126 #define MCFGPIO_PCLRR_TIMER 0xFC0A4029 127 #define MCFGPIO_PCLRR_UART 0xFC0A402A 128 #define MCFGPIO_PCLRR_FECH 0xFC0A402B 129 #define MCFGPIO_PCLRR_FECL 0xFC0A402C 130 131 /* 132 * Generic GPIO support 133 */ 134 #define MCFGPIO_PODR MCFGPIO_PODR_CS 135 #define MCFGPIO_PDDR MCFGPIO_PDDR_CS 136 #define MCFGPIO_PPDR MCFGPIO_PPDSDR_CS 137 #define MCFGPIO_SETR MCFGPIO_PPDSDR_CS 138 #define MCFGPIO_CLRR MCFGPIO_PCLRR_CS 139 140 #define MCFGPIO_PIN_MAX 80 141 #define MCFGPIO_IRQ_MAX 8 142 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 143 144 #define MCF_GPIO_PAR_UART 0xFC0A4036 145 #define MCF_GPIO_PAR_FECI2C 0xFC0A4033 146 #define MCF_GPIO_PAR_QSPI 0xFC0A4034 147 #define MCF_GPIO_PAR_FEC 0xFC0A4038 148 149 #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) 150 #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) 151 152 #define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040) 153 #define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080) 154 155 #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) 156 #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) 157 158 /* 159 * PIT timer module. 160 */ 161 #define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */ 162 #define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */ 163 164 /* 165 * UART module. 166 */ 167 #define MCFUART_BASE0 0xFC060000 /* Base address of UART0 */ 168 #define MCFUART_BASE1 0xFC064000 /* Base address of UART1 */ 169 #define MCFUART_BASE2 0xFC068000 /* Base address of UART2 */ 170 171 /* 172 * FEC module. 173 */ 174 #define MCFFEC_BASE0 0xFC030000 /* Base of FEC ethernet */ 175 #define MCFFEC_SIZE0 0x800 /* Register set size */ 176 177 /* 178 * QSPI module. 179 */ 180 #define MCFQSPI_BASE 0xFC05C000 /* Base of QSPI module */ 181 #define MCFQSPI_SIZE 0x40 /* Register set size */ 182 183 #define MCFQSPI_CS0 46 184 #define MCFQSPI_CS1 47 185 #define MCFQSPI_CS2 27 186 187 /* 188 * Reset Control Unit. 189 */ 190 #define MCF_RCR 0xFC0A0000 191 #define MCF_RSR 0xFC0A0001 192 193 #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 194 #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 195 196 /* 197 * Power Management. 198 */ 199 #define MCFPM_WCR 0xfc040013 200 #define MCFPM_PPMSR0 0xfc04002c 201 #define MCFPM_PPMCR0 0xfc04002d 202 #define MCFPM_PPMHR0 0xfc040030 203 #define MCFPM_PPMLR0 0xfc040034 204 #define MCFPM_LPCR 0xfc0a0007 205 206 /* 207 * I2C module. 208 */ 209 #define MCFI2C_BASE0 0xFC058000 210 #define MCFI2C_SIZE0 0x40 211 212 /****************************************************************************/ 213 #endif /* m520xsim_h */ 214