149148020SSam Ravnborg /****************************************************************************/ 249148020SSam Ravnborg 349148020SSam Ravnborg /* 449148020SSam Ravnborg * m520xsim.h -- ColdFire 5207/5208 System Integration Module support. 549148020SSam Ravnborg * 649148020SSam Ravnborg * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com) 749148020SSam Ravnborg */ 849148020SSam Ravnborg 949148020SSam Ravnborg /****************************************************************************/ 1049148020SSam Ravnborg #ifndef m520xsim_h 1149148020SSam Ravnborg #define m520xsim_h 1249148020SSam Ravnborg /****************************************************************************/ 1349148020SSam Ravnborg 1449148020SSam Ravnborg 1549148020SSam Ravnborg /* 1649148020SSam Ravnborg * Define the 5282 SIM register set addresses. 1749148020SSam Ravnborg */ 1849148020SSam Ravnborg #define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */ 1949148020SSam Ravnborg #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 2049148020SSam Ravnborg #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 2149148020SSam Ravnborg #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 2249148020SSam Ravnborg #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 2349148020SSam Ravnborg #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 2449148020SSam Ravnborg #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 25cd3dd406SGreg Ungerer #define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */ 26cd3dd406SGreg Ungerer #define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */ 2749148020SSam Ravnborg #define MCFINTC_ICR0 0x40 /* Base ICR register */ 2849148020SSam Ravnborg 2949148020SSam Ravnborg #define MCFINT_VECBASE 64 3049148020SSam Ravnborg #define MCFINT_UART0 26 /* Interrupt number for UART0 */ 3149148020SSam Ravnborg #define MCFINT_UART1 27 /* Interrupt number for UART1 */ 3249148020SSam Ravnborg #define MCFINT_UART2 28 /* Interrupt number for UART2 */ 3349148020SSam Ravnborg #define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 3449148020SSam Ravnborg #define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ 3549148020SSam Ravnborg 3649148020SSam Ravnborg /* 3749148020SSam Ravnborg * SDRAM configuration registers. 3849148020SSam Ravnborg */ 3949148020SSam Ravnborg #define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */ 4049148020SSam Ravnborg #define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */ 4149148020SSam Ravnborg #define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */ 4249148020SSam Ravnborg #define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */ 4349148020SSam Ravnborg #define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */ 4449148020SSam Ravnborg #define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */ 4549148020SSam Ravnborg 46afde8560Ssfking@fdwdc.com #define MCFEPORT_EPDDR 0xFC088002 47afde8560Ssfking@fdwdc.com #define MCFEPORT_EPDR 0xFC088004 48afde8560Ssfking@fdwdc.com #define MCFEPORT_EPPDR 0xFC088005 49afde8560Ssfking@fdwdc.com 50afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_BUSCTL 0xFC0A4000 51afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_BE 0xFC0A4001 52afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_CS 0xFC0A4002 53afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_FECI2C 0xFC0A4003 54afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_QSPI 0xFC0A4004 55afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMER 0xFC0A4005 56afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_UART 0xFC0A4006 57afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_FECH 0xFC0A4007 58afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_FECL 0xFC0A4008 59afde8560Ssfking@fdwdc.com 60afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_BUSCTL 0xFC0A400C 61afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_BE 0xFC0A400D 62afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_CS 0xFC0A400E 63afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECI2C 0xFC0A400F 64afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_QSPI 0xFC0A4010 65afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMER 0xFC0A4011 66afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_UART 0xFC0A4012 67afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECH 0xFC0A4013 68afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECL 0xFC0A4014 69afde8560Ssfking@fdwdc.com 70afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BUSCTL 0xFC0A401A 71afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BE 0xFC0A401B 72afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_CS 0xFC0A401C 73afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FECI2C 0xFC0A401D 74afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_QSPI 0xFC0A401E 75afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_TIMER 0xFC0A401F 76afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UART 0xFC0A4021 77afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FECH 0xFC0A4021 78afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FECL 0xFC0A4022 79afde8560Ssfking@fdwdc.com 80afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024 81afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BE 0xFC0A4025 82afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_CS 0xFC0A4026 83afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECI2C 0xFC0A4027 84afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_QSPI 0xFC0A4028 85afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMER 0xFC0A4029 86afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UART 0xFC0A402A 87afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECH 0xFC0A402B 88afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECL 0xFC0A402C 89afde8560Ssfking@fdwdc.com /* 90afde8560Ssfking@fdwdc.com * Generic GPIO support 91afde8560Ssfking@fdwdc.com */ 92afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL 93afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL 94afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL 95afde8560Ssfking@fdwdc.com #define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL 96afde8560Ssfking@fdwdc.com #define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL 97afde8560Ssfking@fdwdc.com 98afde8560Ssfking@fdwdc.com #define MCFGPIO_PIN_MAX 80 99afde8560Ssfking@fdwdc.com #define MCFGPIO_IRQ_MAX 8 100afde8560Ssfking@fdwdc.com #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 101afde8560Ssfking@fdwdc.com /****************************************************************************/ 10249148020SSam Ravnborg 10349148020SSam Ravnborg #define MCF_GPIO_PAR_UART (0xA4036) 10449148020SSam Ravnborg #define MCF_GPIO_PAR_FECI2C (0xA4033) 10549148020SSam Ravnborg #define MCF_GPIO_PAR_FEC (0xA4038) 10649148020SSam Ravnborg 10749148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) 10849148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) 10949148020SSam Ravnborg 11049148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040) 11149148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080) 11249148020SSam Ravnborg 11349148020SSam Ravnborg #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) 11449148020SSam Ravnborg #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) 11549148020SSam Ravnborg 11649148020SSam Ravnborg #define ICR_INTRCONF 0x05 11749148020SSam Ravnborg #define MCFPIT_IMR MCFINTC_IMRL 11849148020SSam Ravnborg #define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1) 11949148020SSam Ravnborg 12025ce4a90SGreg Ungerer /* 12125ce4a90SGreg Ungerer * Reset Controll Unit. 12225ce4a90SGreg Ungerer */ 12325ce4a90SGreg Ungerer #define MCF_RCR 0xFC0A0000 12425ce4a90SGreg Ungerer #define MCF_RSR 0xFC0A0001 12525ce4a90SGreg Ungerer 12625ce4a90SGreg Ungerer #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 12725ce4a90SGreg Ungerer #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 12825ce4a90SGreg Ungerer 12949148020SSam Ravnborg /****************************************************************************/ 13049148020SSam Ravnborg #endif /* m520xsim_h */ 131