149148020SSam Ravnborg /****************************************************************************/ 249148020SSam Ravnborg 349148020SSam Ravnborg /* 449148020SSam Ravnborg * m520xsim.h -- ColdFire 5207/5208 System Integration Module support. 549148020SSam Ravnborg * 649148020SSam Ravnborg * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com) 749148020SSam Ravnborg */ 849148020SSam Ravnborg 949148020SSam Ravnborg /****************************************************************************/ 1049148020SSam Ravnborg #ifndef m520xsim_h 1149148020SSam Ravnborg #define m520xsim_h 1249148020SSam Ravnborg /****************************************************************************/ 1349148020SSam Ravnborg 147fc82b65SGreg Ungerer #define CPU_NAME "COLDFIRE(m520x)" 15733f31b7SGreg Ungerer #define CPU_INSTR_PER_JIFFY 3 16ce3de78aSGreg Ungerer #define MCF_BUSCLK (MCF_CLK / 2) 177fc82b65SGreg Ungerer 18a12cf0a8SGreg Ungerer #include <asm/m52xxacr.h> 19a12cf0a8SGreg Ungerer 2049148020SSam Ravnborg /* 21277c5e3eSGreg Ungerer * Define the 520x SIM register set addresses. 2249148020SSam Ravnborg */ 23571f0608SGreg Ungerer #define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */ 2449148020SSam Ravnborg #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 2549148020SSam Ravnborg #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 2649148020SSam Ravnborg #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 2749148020SSam Ravnborg #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 2849148020SSam Ravnborg #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 2949148020SSam Ravnborg #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 30cd3dd406SGreg Ungerer #define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */ 31cd3dd406SGreg Ungerer #define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */ 3249148020SSam Ravnborg #define MCFINTC_ICR0 0x40 /* Base ICR register */ 3349148020SSam Ravnborg 34277c5e3eSGreg Ungerer /* 35277c5e3eSGreg Ungerer * The common interrupt controller code just wants to know the absolute 36277c5e3eSGreg Ungerer * address to the SIMR and CIMR registers (not offsets into IPSBAR). 37277c5e3eSGreg Ungerer * The 520x family only has a single INTC unit. 38277c5e3eSGreg Ungerer */ 39571f0608SGreg Ungerer #define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR) 40571f0608SGreg Ungerer #define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR) 41571f0608SGreg Ungerer #define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0) 42277c5e3eSGreg Ungerer #define MCFINTC1_SIMR (0) 43277c5e3eSGreg Ungerer #define MCFINTC1_CIMR (0) 44277c5e3eSGreg Ungerer #define MCFINTC1_ICR0 (0) 45277c5e3eSGreg Ungerer 4649148020SSam Ravnborg #define MCFINT_VECBASE 64 4749148020SSam Ravnborg #define MCFINT_UART0 26 /* Interrupt number for UART0 */ 4849148020SSam Ravnborg #define MCFINT_UART1 27 /* Interrupt number for UART1 */ 4949148020SSam Ravnborg #define MCFINT_UART2 28 /* Interrupt number for UART2 */ 5049148020SSam Ravnborg #define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 51d4e08372SGreg Ungerer #define MCFINT_FECRX0 36 /* Interrupt number for FEC RX */ 52d4e08372SGreg Ungerer #define MCFINT_FECTX0 40 /* Interrupt number for FEC RX */ 53d4e08372SGreg Ungerer #define MCFINT_FECENTC0 42 /* Interrupt number for FEC RX */ 5449148020SSam Ravnborg #define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ 5549148020SSam Ravnborg 56ffc203bcSGreg Ungerer #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) 57ffc203bcSGreg Ungerer #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) 58ffc203bcSGreg Ungerer #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) 59ffc203bcSGreg Ungerer 60d4e08372SGreg Ungerer #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) 61d4e08372SGreg Ungerer #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) 62d4e08372SGreg Ungerer #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 63d4e08372SGreg Ungerer 64a4e2e2acSGreg Ungerer #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 65a4e2e2acSGreg Ungerer 6649148020SSam Ravnborg /* 6749148020SSam Ravnborg * SDRAM configuration registers. 6849148020SSam Ravnborg */ 69571f0608SGreg Ungerer #define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */ 70571f0608SGreg Ungerer #define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */ 71571f0608SGreg Ungerer #define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */ 72571f0608SGreg Ungerer #define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */ 73571f0608SGreg Ungerer #define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */ 74571f0608SGreg Ungerer #define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */ 7549148020SSam Ravnborg 76a12cf0a8SGreg Ungerer /* 77a12cf0a8SGreg Ungerer * EPORT and GPIO registers. 78a12cf0a8SGreg Ungerer */ 7947e0c7e1SGreg Ungerer #define MCFEPORT_EPPAR 0xFC088000 80afde8560Ssfking@fdwdc.com #define MCFEPORT_EPDDR 0xFC088002 8147e0c7e1SGreg Ungerer #define MCFEPORT_EPIER 0xFC088003 82afde8560Ssfking@fdwdc.com #define MCFEPORT_EPDR 0xFC088004 83afde8560Ssfking@fdwdc.com #define MCFEPORT_EPPDR 0xFC088005 8447e0c7e1SGreg Ungerer #define MCFEPORT_EPFR 0xFC088006 85afde8560Ssfking@fdwdc.com 86afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_BUSCTL 0xFC0A4000 87afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_BE 0xFC0A4001 88afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_CS 0xFC0A4002 89afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_FECI2C 0xFC0A4003 90afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_QSPI 0xFC0A4004 91afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMER 0xFC0A4005 92afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_UART 0xFC0A4006 93afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_FECH 0xFC0A4007 94afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_FECL 0xFC0A4008 95afde8560Ssfking@fdwdc.com 96afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_BUSCTL 0xFC0A400C 97afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_BE 0xFC0A400D 98afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_CS 0xFC0A400E 99afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECI2C 0xFC0A400F 100afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_QSPI 0xFC0A4010 101afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMER 0xFC0A4011 102afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_UART 0xFC0A4012 103afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECH 0xFC0A4013 104afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECL 0xFC0A4014 105afde8560Ssfking@fdwdc.com 10689127ed3SPeter Turczak #define MCFGPIO_PPDSDR_CS 0xFC0A401A 10789127ed3SPeter Turczak #define MCFGPIO_PPDSDR_FECI2C 0xFC0A401B 10889127ed3SPeter Turczak #define MCFGPIO_PPDSDR_QSPI 0xFC0A401C 10989127ed3SPeter Turczak #define MCFGPIO_PPDSDR_TIMER 0xFC0A401D 11089127ed3SPeter Turczak #define MCFGPIO_PPDSDR_UART 0xFC0A401E 11189127ed3SPeter Turczak #define MCFGPIO_PPDSDR_FECH 0xFC0A401F 11289127ed3SPeter Turczak #define MCFGPIO_PPDSDR_FECL 0xFC0A4020 113afde8560Ssfking@fdwdc.com 114afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024 115afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BE 0xFC0A4025 116afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_CS 0xFC0A4026 117afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECI2C 0xFC0A4027 118afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_QSPI 0xFC0A4028 119afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMER 0xFC0A4029 120afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UART 0xFC0A402A 121afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECH 0xFC0A402B 122afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECL 0xFC0A402C 12357015421SGreg Ungerer 124afde8560Ssfking@fdwdc.com /* 125afde8560Ssfking@fdwdc.com * Generic GPIO support 126afde8560Ssfking@fdwdc.com */ 12789127ed3SPeter Turczak #define MCFGPIO_PODR MCFGPIO_PODR_CS 12889127ed3SPeter Turczak #define MCFGPIO_PDDR MCFGPIO_PDDR_CS 12989127ed3SPeter Turczak #define MCFGPIO_PPDR MCFGPIO_PPDSDR_CS 13089127ed3SPeter Turczak #define MCFGPIO_SETR MCFGPIO_PPDSDR_CS 13189127ed3SPeter Turczak #define MCFGPIO_CLRR MCFGPIO_PCLRR_CS 132afde8560Ssfking@fdwdc.com 133afde8560Ssfking@fdwdc.com #define MCFGPIO_PIN_MAX 80 134afde8560Ssfking@fdwdc.com #define MCFGPIO_IRQ_MAX 8 135afde8560Ssfking@fdwdc.com #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 13649148020SSam Ravnborg 137571f0608SGreg Ungerer #define MCF_GPIO_PAR_UART 0xFC0A4036 138571f0608SGreg Ungerer #define MCF_GPIO_PAR_FECI2C 0xFC0A4033 139571f0608SGreg Ungerer #define MCF_GPIO_PAR_QSPI 0xFC0A4034 140571f0608SGreg Ungerer #define MCF_GPIO_PAR_FEC 0xFC0A4038 14149148020SSam Ravnborg 14249148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) 14349148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) 14449148020SSam Ravnborg 14549148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040) 14649148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080) 14749148020SSam Ravnborg 14849148020SSam Ravnborg #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) 14949148020SSam Ravnborg #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) 15049148020SSam Ravnborg 15125ce4a90SGreg Ungerer /* 152f317c71aSGreg Ungerer * PIT timer module. 153f317c71aSGreg Ungerer */ 154f317c71aSGreg Ungerer #define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */ 155f317c71aSGreg Ungerer #define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */ 156f317c71aSGreg Ungerer 157f317c71aSGreg Ungerer /* 15857015421SGreg Ungerer * UART module. 15957015421SGreg Ungerer */ 160ffc203bcSGreg Ungerer #define MCFUART_BASE0 0xFC060000 /* Base address of UART0 */ 161ffc203bcSGreg Ungerer #define MCFUART_BASE1 0xFC064000 /* Base address of UART1 */ 162ffc203bcSGreg Ungerer #define MCFUART_BASE2 0xFC068000 /* Base address of UART2 */ 163571f0608SGreg Ungerer 164571f0608SGreg Ungerer /* 165571f0608SGreg Ungerer * FEC module. 166571f0608SGreg Ungerer */ 167d4e08372SGreg Ungerer #define MCFFEC_BASE0 0xFC030000 /* Base of FEC ethernet */ 168d4e08372SGreg Ungerer #define MCFFEC_SIZE0 0x800 /* Register set size */ 16957015421SGreg Ungerer 17057015421SGreg Ungerer /* 171a4e2e2acSGreg Ungerer * QSPI module. 172a4e2e2acSGreg Ungerer */ 173a4e2e2acSGreg Ungerer #define MCFQSPI_BASE 0xFC05C000 /* Base of QSPI module */ 174a4e2e2acSGreg Ungerer #define MCFQSPI_SIZE 0x40 /* Register set size */ 175a4e2e2acSGreg Ungerer 176a4e2e2acSGreg Ungerer #define MCFQSPI_CS0 46 177a4e2e2acSGreg Ungerer #define MCFQSPI_CS1 47 178a4e2e2acSGreg Ungerer #define MCFQSPI_CS2 27 179a4e2e2acSGreg Ungerer 180a4e2e2acSGreg Ungerer /* 18125985edcSLucas De Marchi * Reset Control Unit. 18225ce4a90SGreg Ungerer */ 18325ce4a90SGreg Ungerer #define MCF_RCR 0xFC0A0000 18425ce4a90SGreg Ungerer #define MCF_RSR 0xFC0A0001 18525ce4a90SGreg Ungerer 18625ce4a90SGreg Ungerer #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 18725ce4a90SGreg Ungerer #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 18825ce4a90SGreg Ungerer 18949148020SSam Ravnborg /****************************************************************************/ 19049148020SSam Ravnborg #endif /* m520xsim_h */ 191