149148020SSam Ravnborg /****************************************************************************/ 249148020SSam Ravnborg 349148020SSam Ravnborg /* 449148020SSam Ravnborg * m520xsim.h -- ColdFire 5207/5208 System Integration Module support. 549148020SSam Ravnborg * 649148020SSam Ravnborg * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com) 749148020SSam Ravnborg */ 849148020SSam Ravnborg 949148020SSam Ravnborg /****************************************************************************/ 1049148020SSam Ravnborg #ifndef m520xsim_h 1149148020SSam Ravnborg #define m520xsim_h 1249148020SSam Ravnborg /****************************************************************************/ 1349148020SSam Ravnborg 147fc82b65SGreg Ungerer #define CPU_NAME "COLDFIRE(m520x)" 15733f31b7SGreg Ungerer #define CPU_INSTR_PER_JIFFY 3 16ce3de78aSGreg Ungerer #define MCF_BUSCLK (MCF_CLK / 2) 177fc82b65SGreg Ungerer 18a12cf0a8SGreg Ungerer #include <asm/m52xxacr.h> 19a12cf0a8SGreg Ungerer 2049148020SSam Ravnborg /* 21277c5e3eSGreg Ungerer * Define the 520x SIM register set addresses. 2249148020SSam Ravnborg */ 23571f0608SGreg Ungerer #define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */ 2449148020SSam Ravnborg #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 2549148020SSam Ravnborg #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 2649148020SSam Ravnborg #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 2749148020SSam Ravnborg #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 2849148020SSam Ravnborg #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 2949148020SSam Ravnborg #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 30cd3dd406SGreg Ungerer #define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */ 31cd3dd406SGreg Ungerer #define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */ 3249148020SSam Ravnborg #define MCFINTC_ICR0 0x40 /* Base ICR register */ 3349148020SSam Ravnborg 34277c5e3eSGreg Ungerer /* 35277c5e3eSGreg Ungerer * The common interrupt controller code just wants to know the absolute 36277c5e3eSGreg Ungerer * address to the SIMR and CIMR registers (not offsets into IPSBAR). 37277c5e3eSGreg Ungerer * The 520x family only has a single INTC unit. 38277c5e3eSGreg Ungerer */ 39571f0608SGreg Ungerer #define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR) 40571f0608SGreg Ungerer #define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR) 41571f0608SGreg Ungerer #define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0) 42277c5e3eSGreg Ungerer #define MCFINTC1_SIMR (0) 43277c5e3eSGreg Ungerer #define MCFINTC1_CIMR (0) 44277c5e3eSGreg Ungerer #define MCFINTC1_ICR0 (0) 45277c5e3eSGreg Ungerer 4649148020SSam Ravnborg #define MCFINT_VECBASE 64 4749148020SSam Ravnborg #define MCFINT_UART0 26 /* Interrupt number for UART0 */ 4849148020SSam Ravnborg #define MCFINT_UART1 27 /* Interrupt number for UART1 */ 4949148020SSam Ravnborg #define MCFINT_UART2 28 /* Interrupt number for UART2 */ 5049148020SSam Ravnborg #define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 5149148020SSam Ravnborg #define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ 5249148020SSam Ravnborg 5349148020SSam Ravnborg /* 5449148020SSam Ravnborg * SDRAM configuration registers. 5549148020SSam Ravnborg */ 56571f0608SGreg Ungerer #define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */ 57571f0608SGreg Ungerer #define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */ 58571f0608SGreg Ungerer #define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */ 59571f0608SGreg Ungerer #define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */ 60571f0608SGreg Ungerer #define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */ 61571f0608SGreg Ungerer #define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */ 6249148020SSam Ravnborg 63a12cf0a8SGreg Ungerer /* 64a12cf0a8SGreg Ungerer * EPORT and GPIO registers. 65a12cf0a8SGreg Ungerer */ 6647e0c7e1SGreg Ungerer #define MCFEPORT_EPPAR 0xFC088000 67afde8560Ssfking@fdwdc.com #define MCFEPORT_EPDDR 0xFC088002 6847e0c7e1SGreg Ungerer #define MCFEPORT_EPIER 0xFC088003 69afde8560Ssfking@fdwdc.com #define MCFEPORT_EPDR 0xFC088004 70afde8560Ssfking@fdwdc.com #define MCFEPORT_EPPDR 0xFC088005 7147e0c7e1SGreg Ungerer #define MCFEPORT_EPFR 0xFC088006 72afde8560Ssfking@fdwdc.com 73afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_BUSCTL 0xFC0A4000 74afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_BE 0xFC0A4001 75afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_CS 0xFC0A4002 76afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_FECI2C 0xFC0A4003 77afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_QSPI 0xFC0A4004 78afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMER 0xFC0A4005 79afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_UART 0xFC0A4006 80afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_FECH 0xFC0A4007 81afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_FECL 0xFC0A4008 82afde8560Ssfking@fdwdc.com 83afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_BUSCTL 0xFC0A400C 84afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_BE 0xFC0A400D 85afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_CS 0xFC0A400E 86afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECI2C 0xFC0A400F 87afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_QSPI 0xFC0A4010 88afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMER 0xFC0A4011 89afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_UART 0xFC0A4012 90afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECH 0xFC0A4013 91afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECL 0xFC0A4014 92afde8560Ssfking@fdwdc.com 9389127ed3SPeter Turczak #define MCFGPIO_PPDSDR_CS 0xFC0A401A 9489127ed3SPeter Turczak #define MCFGPIO_PPDSDR_FECI2C 0xFC0A401B 9589127ed3SPeter Turczak #define MCFGPIO_PPDSDR_QSPI 0xFC0A401C 9689127ed3SPeter Turczak #define MCFGPIO_PPDSDR_TIMER 0xFC0A401D 9789127ed3SPeter Turczak #define MCFGPIO_PPDSDR_UART 0xFC0A401E 9889127ed3SPeter Turczak #define MCFGPIO_PPDSDR_FECH 0xFC0A401F 9989127ed3SPeter Turczak #define MCFGPIO_PPDSDR_FECL 0xFC0A4020 100afde8560Ssfking@fdwdc.com 101afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024 102afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BE 0xFC0A4025 103afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_CS 0xFC0A4026 104afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECI2C 0xFC0A4027 105afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_QSPI 0xFC0A4028 106afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMER 0xFC0A4029 107afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UART 0xFC0A402A 108afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECH 0xFC0A402B 109afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECL 0xFC0A402C 11057015421SGreg Ungerer 111afde8560Ssfking@fdwdc.com /* 112afde8560Ssfking@fdwdc.com * Generic GPIO support 113afde8560Ssfking@fdwdc.com */ 11489127ed3SPeter Turczak #define MCFGPIO_PODR MCFGPIO_PODR_CS 11589127ed3SPeter Turczak #define MCFGPIO_PDDR MCFGPIO_PDDR_CS 11689127ed3SPeter Turczak #define MCFGPIO_PPDR MCFGPIO_PPDSDR_CS 11789127ed3SPeter Turczak #define MCFGPIO_SETR MCFGPIO_PPDSDR_CS 11889127ed3SPeter Turczak #define MCFGPIO_CLRR MCFGPIO_PCLRR_CS 119afde8560Ssfking@fdwdc.com 120afde8560Ssfking@fdwdc.com #define MCFGPIO_PIN_MAX 80 121afde8560Ssfking@fdwdc.com #define MCFGPIO_IRQ_MAX 8 122afde8560Ssfking@fdwdc.com #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 12349148020SSam Ravnborg 124571f0608SGreg Ungerer #define MCF_GPIO_PAR_UART 0xFC0A4036 125571f0608SGreg Ungerer #define MCF_GPIO_PAR_FECI2C 0xFC0A4033 126571f0608SGreg Ungerer #define MCF_GPIO_PAR_QSPI 0xFC0A4034 127571f0608SGreg Ungerer #define MCF_GPIO_PAR_FEC 0xFC0A4038 12849148020SSam Ravnborg 12949148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) 13049148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) 13149148020SSam Ravnborg 13249148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040) 13349148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080) 13449148020SSam Ravnborg 13549148020SSam Ravnborg #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) 13649148020SSam Ravnborg #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) 13749148020SSam Ravnborg 13825ce4a90SGreg Ungerer /* 139f317c71aSGreg Ungerer * PIT timer module. 140f317c71aSGreg Ungerer */ 141f317c71aSGreg Ungerer #define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */ 142f317c71aSGreg Ungerer #define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */ 143f317c71aSGreg Ungerer 144f317c71aSGreg Ungerer /* 14557015421SGreg Ungerer * UART module. 14657015421SGreg Ungerer */ 147571f0608SGreg Ungerer #define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */ 148571f0608SGreg Ungerer #define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */ 149571f0608SGreg Ungerer #define MCFUART_BASE3 0xFC068000 /* Base address of UART2 */ 150571f0608SGreg Ungerer 151571f0608SGreg Ungerer /* 152571f0608SGreg Ungerer * FEC module. 153571f0608SGreg Ungerer */ 154571f0608SGreg Ungerer #define MCFFEC_BASE 0xFC030000 /* Base of FEC ethernet */ 155571f0608SGreg Ungerer #define MCFFEC_SIZE 0x800 /* Register set size */ 15657015421SGreg Ungerer 15757015421SGreg Ungerer /* 15825985edcSLucas De Marchi * Reset Control Unit. 15925ce4a90SGreg Ungerer */ 16025ce4a90SGreg Ungerer #define MCF_RCR 0xFC0A0000 16125ce4a90SGreg Ungerer #define MCF_RSR 0xFC0A0001 16225ce4a90SGreg Ungerer 16325ce4a90SGreg Ungerer #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 16425ce4a90SGreg Ungerer #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 16525ce4a90SGreg Ungerer 16649148020SSam Ravnborg /****************************************************************************/ 16749148020SSam Ravnborg #endif /* m520xsim_h */ 168