149148020SSam Ravnborg /****************************************************************************/ 249148020SSam Ravnborg 349148020SSam Ravnborg /* 449148020SSam Ravnborg * m520xsim.h -- ColdFire 5207/5208 System Integration Module support. 549148020SSam Ravnborg * 649148020SSam Ravnborg * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com) 749148020SSam Ravnborg */ 849148020SSam Ravnborg 949148020SSam Ravnborg /****************************************************************************/ 1049148020SSam Ravnborg #ifndef m520xsim_h 1149148020SSam Ravnborg #define m520xsim_h 1249148020SSam Ravnborg /****************************************************************************/ 1349148020SSam Ravnborg 147fc82b65SGreg Ungerer #define CPU_NAME "COLDFIRE(m520x)" 15733f31b7SGreg Ungerer #define CPU_INSTR_PER_JIFFY 3 167fc82b65SGreg Ungerer 1749148020SSam Ravnborg /* 18277c5e3eSGreg Ungerer * Define the 520x SIM register set addresses. 1949148020SSam Ravnborg */ 2049148020SSam Ravnborg #define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */ 2149148020SSam Ravnborg #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 2249148020SSam Ravnborg #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 2349148020SSam Ravnborg #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 2449148020SSam Ravnborg #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 2549148020SSam Ravnborg #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 2649148020SSam Ravnborg #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 27cd3dd406SGreg Ungerer #define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */ 28cd3dd406SGreg Ungerer #define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */ 2949148020SSam Ravnborg #define MCFINTC_ICR0 0x40 /* Base ICR register */ 3049148020SSam Ravnborg 31277c5e3eSGreg Ungerer /* 32277c5e3eSGreg Ungerer * The common interrupt controller code just wants to know the absolute 33277c5e3eSGreg Ungerer * address to the SIMR and CIMR registers (not offsets into IPSBAR). 34277c5e3eSGreg Ungerer * The 520x family only has a single INTC unit. 35277c5e3eSGreg Ungerer */ 36277c5e3eSGreg Ungerer #define MCFINTC0_SIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR) 37277c5e3eSGreg Ungerer #define MCFINTC0_CIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR) 38277c5e3eSGreg Ungerer #define MCFINTC0_ICR0 (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0) 39277c5e3eSGreg Ungerer #define MCFINTC1_SIMR (0) 40277c5e3eSGreg Ungerer #define MCFINTC1_CIMR (0) 41277c5e3eSGreg Ungerer #define MCFINTC1_ICR0 (0) 42277c5e3eSGreg Ungerer 4349148020SSam Ravnborg #define MCFINT_VECBASE 64 4449148020SSam Ravnborg #define MCFINT_UART0 26 /* Interrupt number for UART0 */ 4549148020SSam Ravnborg #define MCFINT_UART1 27 /* Interrupt number for UART1 */ 4649148020SSam Ravnborg #define MCFINT_UART2 28 /* Interrupt number for UART2 */ 4749148020SSam Ravnborg #define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 4849148020SSam Ravnborg #define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ 4949148020SSam Ravnborg 5049148020SSam Ravnborg /* 5149148020SSam Ravnborg * SDRAM configuration registers. 5249148020SSam Ravnborg */ 5349148020SSam Ravnborg #define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */ 5449148020SSam Ravnborg #define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */ 5549148020SSam Ravnborg #define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */ 5649148020SSam Ravnborg #define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */ 5749148020SSam Ravnborg #define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */ 5849148020SSam Ravnborg #define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */ 5949148020SSam Ravnborg 60afde8560Ssfking@fdwdc.com #define MCFEPORT_EPDDR 0xFC088002 61afde8560Ssfking@fdwdc.com #define MCFEPORT_EPDR 0xFC088004 62afde8560Ssfking@fdwdc.com #define MCFEPORT_EPPDR 0xFC088005 63afde8560Ssfking@fdwdc.com 64afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_BUSCTL 0xFC0A4000 65afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_BE 0xFC0A4001 66afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_CS 0xFC0A4002 67afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_FECI2C 0xFC0A4003 68afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_QSPI 0xFC0A4004 69afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMER 0xFC0A4005 70afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_UART 0xFC0A4006 71afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_FECH 0xFC0A4007 72afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_FECL 0xFC0A4008 73afde8560Ssfking@fdwdc.com 74afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_BUSCTL 0xFC0A400C 75afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_BE 0xFC0A400D 76afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_CS 0xFC0A400E 77afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECI2C 0xFC0A400F 78afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_QSPI 0xFC0A4010 79afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMER 0xFC0A4011 80afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_UART 0xFC0A4012 81afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECH 0xFC0A4013 82afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECL 0xFC0A4014 83afde8560Ssfking@fdwdc.com 84afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BUSCTL 0xFC0A401A 85afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BE 0xFC0A401B 86afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_CS 0xFC0A401C 87afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FECI2C 0xFC0A401D 88afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_QSPI 0xFC0A401E 89afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_TIMER 0xFC0A401F 90afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UART 0xFC0A4021 91afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FECH 0xFC0A4021 92afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FECL 0xFC0A4022 93afde8560Ssfking@fdwdc.com 94afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024 95afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BE 0xFC0A4025 96afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_CS 0xFC0A4026 97afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECI2C 0xFC0A4027 98afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_QSPI 0xFC0A4028 99afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMER 0xFC0A4029 100afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UART 0xFC0A402A 101afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECH 0xFC0A402B 102afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECL 0xFC0A402C 10357015421SGreg Ungerer 104afde8560Ssfking@fdwdc.com /* 105afde8560Ssfking@fdwdc.com * Generic GPIO support 106afde8560Ssfking@fdwdc.com */ 107afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL 108afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL 109afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL 110afde8560Ssfking@fdwdc.com #define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL 111afde8560Ssfking@fdwdc.com #define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL 112afde8560Ssfking@fdwdc.com 113afde8560Ssfking@fdwdc.com #define MCFGPIO_PIN_MAX 80 114afde8560Ssfking@fdwdc.com #define MCFGPIO_IRQ_MAX 8 115afde8560Ssfking@fdwdc.com #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 11649148020SSam Ravnborg 11749148020SSam Ravnborg #define MCF_GPIO_PAR_UART (0xA4036) 11849148020SSam Ravnborg #define MCF_GPIO_PAR_FECI2C (0xA4033) 11991d60417SSteven King #define MCF_GPIO_PAR_QSPI (0xA4034) 12049148020SSam Ravnborg #define MCF_GPIO_PAR_FEC (0xA4038) 12149148020SSam Ravnborg 12249148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) 12349148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) 12449148020SSam Ravnborg 12549148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040) 12649148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080) 12749148020SSam Ravnborg 12849148020SSam Ravnborg #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) 12949148020SSam Ravnborg #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) 13049148020SSam Ravnborg 13125ce4a90SGreg Ungerer /* 13257015421SGreg Ungerer * UART module. 13357015421SGreg Ungerer */ 13457015421SGreg Ungerer #define MCFUART_BASE1 0x60000 /* Base address of UART1 */ 13557015421SGreg Ungerer #define MCFUART_BASE2 0x64000 /* Base address of UART2 */ 13657015421SGreg Ungerer #define MCFUART_BASE3 0x68000 /* Base address of UART2 */ 13757015421SGreg Ungerer 13857015421SGreg Ungerer /* 13925ce4a90SGreg Ungerer * Reset Controll Unit. 14025ce4a90SGreg Ungerer */ 14125ce4a90SGreg Ungerer #define MCF_RCR 0xFC0A0000 14225ce4a90SGreg Ungerer #define MCF_RSR 0xFC0A0001 14325ce4a90SGreg Ungerer 14425ce4a90SGreg Ungerer #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 14525ce4a90SGreg Ungerer #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 14625ce4a90SGreg Ungerer 14749148020SSam Ravnborg /****************************************************************************/ 14849148020SSam Ravnborg #endif /* m520xsim_h */ 149