149148020SSam Ravnborg /****************************************************************************/ 249148020SSam Ravnborg 349148020SSam Ravnborg /* 449148020SSam Ravnborg * m520xsim.h -- ColdFire 5207/5208 System Integration Module support. 549148020SSam Ravnborg * 649148020SSam Ravnborg * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com) 749148020SSam Ravnborg */ 849148020SSam Ravnborg 949148020SSam Ravnborg /****************************************************************************/ 1049148020SSam Ravnborg #ifndef m520xsim_h 1149148020SSam Ravnborg #define m520xsim_h 1249148020SSam Ravnborg /****************************************************************************/ 1349148020SSam Ravnborg 1449148020SSam Ravnborg /* 15277c5e3eSGreg Ungerer * Define the 520x SIM register set addresses. 1649148020SSam Ravnborg */ 1749148020SSam Ravnborg #define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */ 1849148020SSam Ravnborg #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 1949148020SSam Ravnborg #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 2049148020SSam Ravnborg #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 2149148020SSam Ravnborg #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 2249148020SSam Ravnborg #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 2349148020SSam Ravnborg #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 24cd3dd406SGreg Ungerer #define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */ 25cd3dd406SGreg Ungerer #define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */ 2649148020SSam Ravnborg #define MCFINTC_ICR0 0x40 /* Base ICR register */ 2749148020SSam Ravnborg 28277c5e3eSGreg Ungerer /* 29277c5e3eSGreg Ungerer * The common interrupt controller code just wants to know the absolute 30277c5e3eSGreg Ungerer * address to the SIMR and CIMR registers (not offsets into IPSBAR). 31277c5e3eSGreg Ungerer * The 520x family only has a single INTC unit. 32277c5e3eSGreg Ungerer */ 33277c5e3eSGreg Ungerer #define MCFINTC0_SIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR) 34277c5e3eSGreg Ungerer #define MCFINTC0_CIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR) 35277c5e3eSGreg Ungerer #define MCFINTC0_ICR0 (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0) 36277c5e3eSGreg Ungerer #define MCFINTC1_SIMR (0) 37277c5e3eSGreg Ungerer #define MCFINTC1_CIMR (0) 38277c5e3eSGreg Ungerer #define MCFINTC1_ICR0 (0) 39277c5e3eSGreg Ungerer 4049148020SSam Ravnborg #define MCFINT_VECBASE 64 4149148020SSam Ravnborg #define MCFINT_UART0 26 /* Interrupt number for UART0 */ 4249148020SSam Ravnborg #define MCFINT_UART1 27 /* Interrupt number for UART1 */ 4349148020SSam Ravnborg #define MCFINT_UART2 28 /* Interrupt number for UART2 */ 4449148020SSam Ravnborg #define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 4549148020SSam Ravnborg #define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ 4649148020SSam Ravnborg 4749148020SSam Ravnborg /* 4849148020SSam Ravnborg * SDRAM configuration registers. 4949148020SSam Ravnborg */ 5049148020SSam Ravnborg #define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */ 5149148020SSam Ravnborg #define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */ 5249148020SSam Ravnborg #define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */ 5349148020SSam Ravnborg #define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */ 5449148020SSam Ravnborg #define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */ 5549148020SSam Ravnborg #define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */ 5649148020SSam Ravnborg 57afde8560Ssfking@fdwdc.com #define MCFEPORT_EPDDR 0xFC088002 58afde8560Ssfking@fdwdc.com #define MCFEPORT_EPDR 0xFC088004 59afde8560Ssfking@fdwdc.com #define MCFEPORT_EPPDR 0xFC088005 60afde8560Ssfking@fdwdc.com 61afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_BUSCTL 0xFC0A4000 62afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_BE 0xFC0A4001 63afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_CS 0xFC0A4002 64afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_FECI2C 0xFC0A4003 65afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_QSPI 0xFC0A4004 66afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMER 0xFC0A4005 67afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_UART 0xFC0A4006 68afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_FECH 0xFC0A4007 69afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR_FECL 0xFC0A4008 70afde8560Ssfking@fdwdc.com 71afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_BUSCTL 0xFC0A400C 72afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_BE 0xFC0A400D 73afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_CS 0xFC0A400E 74afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECI2C 0xFC0A400F 75afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_QSPI 0xFC0A4010 76afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMER 0xFC0A4011 77afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_UART 0xFC0A4012 78afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECH 0xFC0A4013 79afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECL 0xFC0A4014 80afde8560Ssfking@fdwdc.com 81afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BUSCTL 0xFC0A401A 82afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BE 0xFC0A401B 83afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_CS 0xFC0A401C 84afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FECI2C 0xFC0A401D 85afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_QSPI 0xFC0A401E 86afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_TIMER 0xFC0A401F 87afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UART 0xFC0A4021 88afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FECH 0xFC0A4021 89afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FECL 0xFC0A4022 90afde8560Ssfking@fdwdc.com 91afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024 92afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BE 0xFC0A4025 93afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_CS 0xFC0A4026 94afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECI2C 0xFC0A4027 95afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_QSPI 0xFC0A4028 96afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMER 0xFC0A4029 97afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UART 0xFC0A402A 98afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECH 0xFC0A402B 99afde8560Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECL 0xFC0A402C 100afde8560Ssfking@fdwdc.com /* 101afde8560Ssfking@fdwdc.com * Generic GPIO support 102afde8560Ssfking@fdwdc.com */ 103afde8560Ssfking@fdwdc.com #define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL 104afde8560Ssfking@fdwdc.com #define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL 105afde8560Ssfking@fdwdc.com #define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL 106afde8560Ssfking@fdwdc.com #define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL 107afde8560Ssfking@fdwdc.com #define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL 108afde8560Ssfking@fdwdc.com 109afde8560Ssfking@fdwdc.com #define MCFGPIO_PIN_MAX 80 110afde8560Ssfking@fdwdc.com #define MCFGPIO_IRQ_MAX 8 111afde8560Ssfking@fdwdc.com #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 112afde8560Ssfking@fdwdc.com /****************************************************************************/ 11349148020SSam Ravnborg 11449148020SSam Ravnborg #define MCF_GPIO_PAR_UART (0xA4036) 11549148020SSam Ravnborg #define MCF_GPIO_PAR_FECI2C (0xA4033) 11649148020SSam Ravnborg #define MCF_GPIO_PAR_FEC (0xA4038) 11749148020SSam Ravnborg 11849148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) 11949148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) 12049148020SSam Ravnborg 12149148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040) 12249148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080) 12349148020SSam Ravnborg 12449148020SSam Ravnborg #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) 12549148020SSam Ravnborg #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) 12649148020SSam Ravnborg 12749148020SSam Ravnborg #define ICR_INTRCONF 0x05 12849148020SSam Ravnborg #define MCFPIT_IMR MCFINTC_IMRL 12949148020SSam Ravnborg #define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1) 13049148020SSam Ravnborg 13125ce4a90SGreg Ungerer /* 13225ce4a90SGreg Ungerer * Reset Controll Unit. 13325ce4a90SGreg Ungerer */ 13425ce4a90SGreg Ungerer #define MCF_RCR 0xFC0A0000 13525ce4a90SGreg Ungerer #define MCF_RSR 0xFC0A0001 13625ce4a90SGreg Ungerer 13725ce4a90SGreg Ungerer #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 13825ce4a90SGreg Ungerer #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 13925ce4a90SGreg Ungerer 14049148020SSam Ravnborg /****************************************************************************/ 14149148020SSam Ravnborg #endif /* m520xsim_h */ 142