149148020SSam Ravnborg /****************************************************************************/ 249148020SSam Ravnborg 349148020SSam Ravnborg /* 449148020SSam Ravnborg * m520xsim.h -- ColdFire 5207/5208 System Integration Module support. 549148020SSam Ravnborg * 649148020SSam Ravnborg * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com) 749148020SSam Ravnborg */ 849148020SSam Ravnborg 949148020SSam Ravnborg /****************************************************************************/ 1049148020SSam Ravnborg #ifndef m520xsim_h 1149148020SSam Ravnborg #define m520xsim_h 1249148020SSam Ravnborg /****************************************************************************/ 1349148020SSam Ravnborg 1449148020SSam Ravnborg 1549148020SSam Ravnborg /* 1649148020SSam Ravnborg * Define the 5282 SIM register set addresses. 1749148020SSam Ravnborg */ 1849148020SSam Ravnborg #define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */ 1949148020SSam Ravnborg #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 2049148020SSam Ravnborg #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 2149148020SSam Ravnborg #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 2249148020SSam Ravnborg #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 2349148020SSam Ravnborg #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 2449148020SSam Ravnborg #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 2549148020SSam Ravnborg #define MCFINTC_ICR0 0x40 /* Base ICR register */ 2649148020SSam Ravnborg 2749148020SSam Ravnborg #define MCFINT_VECBASE 64 2849148020SSam Ravnborg #define MCFINT_UART0 26 /* Interrupt number for UART0 */ 2949148020SSam Ravnborg #define MCFINT_UART1 27 /* Interrupt number for UART1 */ 3049148020SSam Ravnborg #define MCFINT_UART2 28 /* Interrupt number for UART2 */ 3149148020SSam Ravnborg #define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 3249148020SSam Ravnborg #define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ 3349148020SSam Ravnborg 3449148020SSam Ravnborg /* 3549148020SSam Ravnborg * SDRAM configuration registers. 3649148020SSam Ravnborg */ 3749148020SSam Ravnborg #define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */ 3849148020SSam Ravnborg #define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */ 3949148020SSam Ravnborg #define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */ 4049148020SSam Ravnborg #define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */ 4149148020SSam Ravnborg #define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */ 4249148020SSam Ravnborg #define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */ 4349148020SSam Ravnborg 4449148020SSam Ravnborg 4549148020SSam Ravnborg #define MCF_GPIO_PAR_UART (0xA4036) 4649148020SSam Ravnborg #define MCF_GPIO_PAR_FECI2C (0xA4033) 4749148020SSam Ravnborg #define MCF_GPIO_PAR_FEC (0xA4038) 4849148020SSam Ravnborg 4949148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) 5049148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) 5149148020SSam Ravnborg 5249148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040) 5349148020SSam Ravnborg #define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080) 5449148020SSam Ravnborg 5549148020SSam Ravnborg #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) 5649148020SSam Ravnborg #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) 5749148020SSam Ravnborg 5849148020SSam Ravnborg #define ICR_INTRCONF 0x05 5949148020SSam Ravnborg #define MCFPIT_IMR MCFINTC_IMRL 6049148020SSam Ravnborg #define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1) 6149148020SSam Ravnborg 6225ce4a90SGreg Ungerer /* 6325ce4a90SGreg Ungerer * Reset Controll Unit. 6425ce4a90SGreg Ungerer */ 6525ce4a90SGreg Ungerer #define MCF_RCR 0xFC0A0000 6625ce4a90SGreg Ungerer #define MCF_RSR 0xFC0A0001 6725ce4a90SGreg Ungerer 6825ce4a90SGreg Ungerer #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 6925ce4a90SGreg Ungerer #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 7025ce4a90SGreg Ungerer 7149148020SSam Ravnborg /****************************************************************************/ 7249148020SSam Ravnborg #endif /* m520xsim_h */ 73