1 /* 2 ** linux/atarihw.h -- This header defines some macros and pointers for 3 ** the various Atari custom hardware registers. 4 ** 5 ** Copyright 1994 by Björn Brauel 6 ** 7 ** 5/1/94 Roman Hodek: 8 ** Added definitions for TT specific chips. 9 ** 10 ** 1996-09-13 lars brinkhoff <f93labr@dd.chalmers.se>: 11 ** Finally added definitions for the matrix/codec and the DSP56001 host 12 ** interface. 13 ** 14 ** This file is subject to the terms and conditions of the GNU General Public 15 ** License. See the file COPYING in the main directory of this archive 16 ** for more details. 17 ** 18 */ 19 20 #ifndef _LINUX_ATARIHW_H_ 21 #define _LINUX_ATARIHW_H_ 22 23 #include <linux/types.h> 24 #include <asm/bootinfo-atari.h> 25 #include <asm/raw_io.h> 26 #include <asm/kmap.h> 27 28 extern u_long atari_mch_cookie; 29 extern u_long atari_mch_type; 30 extern u_long atari_switches; 31 extern int atari_rtc_year_offset; 32 extern int atari_dont_touch_floppy_select; 33 34 extern int atari_SCC_reset_done; 35 36 extern ssize_t atari_nvram_read(char *, size_t, loff_t *); 37 extern ssize_t atari_nvram_write(char *, size_t, loff_t *); 38 extern ssize_t atari_nvram_get_size(void); 39 extern long atari_nvram_set_checksum(void); 40 extern long atari_nvram_initialize(void); 41 42 /* convenience macros for testing machine type */ 43 #define MACH_IS_ST ((atari_mch_cookie >> 16) == ATARI_MCH_ST) 44 #define MACH_IS_STE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \ 45 (atari_mch_cookie & 0xffff) == 0) 46 #define MACH_IS_MSTE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \ 47 (atari_mch_cookie & 0xffff) == 0x10) 48 #define MACH_IS_TT ((atari_mch_cookie >> 16) == ATARI_MCH_TT) 49 #define MACH_IS_FALCON ((atari_mch_cookie >> 16) == ATARI_MCH_FALCON) 50 #define MACH_IS_MEDUSA (atari_mch_type == ATARI_MACH_MEDUSA) 51 #define MACH_IS_AB40 (atari_mch_type == ATARI_MACH_AB40) 52 53 /* values for atari_switches */ 54 #define ATARI_SWITCH_IKBD 0x01 55 #define ATARI_SWITCH_MIDI 0x02 56 #define ATARI_SWITCH_SND6 0x04 57 #define ATARI_SWITCH_SND7 0x08 58 #define ATARI_SWITCH_OVSC_SHIFT 16 59 #define ATARI_SWITCH_OVSC_IKBD (ATARI_SWITCH_IKBD << ATARI_SWITCH_OVSC_SHIFT) 60 #define ATARI_SWITCH_OVSC_MIDI (ATARI_SWITCH_MIDI << ATARI_SWITCH_OVSC_SHIFT) 61 #define ATARI_SWITCH_OVSC_SND6 (ATARI_SWITCH_SND6 << ATARI_SWITCH_OVSC_SHIFT) 62 #define ATARI_SWITCH_OVSC_SND7 (ATARI_SWITCH_SND7 << ATARI_SWITCH_OVSC_SHIFT) 63 #define ATARI_SWITCH_OVSC_MASK 0xffff0000 64 65 /* 66 * Define several Hardware-Chips for indication so that for the ATARI we do 67 * no longer decide whether it is a Falcon or other machine . It's just 68 * important what hardware the machine uses 69 */ 70 71 /* ++roman 08/08/95: rewritten from ORing constants to a C bitfield */ 72 73 #define ATARIHW_DECLARE(name) unsigned name : 1 74 #define ATARIHW_SET(name) (atari_hw_present.name = 1) 75 #define ATARIHW_PRESENT(name) (atari_hw_present.name) 76 77 struct atari_hw_present { 78 /* video hardware */ 79 ATARIHW_DECLARE(STND_SHIFTER); /* ST-Shifter - no base low ! */ 80 ATARIHW_DECLARE(EXTD_SHIFTER); /* STe-Shifter - 24 bit address */ 81 ATARIHW_DECLARE(TT_SHIFTER); /* TT-Shifter */ 82 ATARIHW_DECLARE(VIDEL_SHIFTER); /* Falcon-Shifter */ 83 /* sound hardware */ 84 ATARIHW_DECLARE(YM_2149); /* Yamaha YM 2149 */ 85 ATARIHW_DECLARE(PCM_8BIT); /* PCM-Sound in STe-ATARI */ 86 ATARIHW_DECLARE(CODEC); /* CODEC Sound (Falcon) */ 87 /* disk storage interfaces */ 88 ATARIHW_DECLARE(TT_SCSI); /* Directly mapped NCR5380 */ 89 ATARIHW_DECLARE(ST_SCSI); /* NCR5380 via ST-DMA (Falcon) */ 90 ATARIHW_DECLARE(ACSI); /* Standard ACSI like in STs */ 91 ATARIHW_DECLARE(IDE); /* IDE Interface */ 92 ATARIHW_DECLARE(FDCSPEED); /* 8/16 MHz switch for FDC */ 93 /* other I/O hardware */ 94 ATARIHW_DECLARE(ST_MFP); /* The ST-MFP (there should be no Atari 95 without it... but who knows?) */ 96 ATARIHW_DECLARE(TT_MFP); /* 2nd MFP */ 97 ATARIHW_DECLARE(SCC); /* Serial Communications Contr. */ 98 ATARIHW_DECLARE(ST_ESCC); /* SCC Z83230 in an ST */ 99 ATARIHW_DECLARE(ANALOG_JOY); /* Paddle Interface for STe 100 and Falcon */ 101 ATARIHW_DECLARE(MICROWIRE); /* Microwire Interface */ 102 /* DMA */ 103 ATARIHW_DECLARE(STND_DMA); /* 24 Bit limited ST-DMA */ 104 ATARIHW_DECLARE(EXTD_DMA); /* 32 Bit ST-DMA */ 105 ATARIHW_DECLARE(SCSI_DMA); /* DMA for the NCR5380 */ 106 ATARIHW_DECLARE(SCC_DMA); /* DMA for the SCC */ 107 /* real time clocks */ 108 ATARIHW_DECLARE(TT_CLK); /* TT compatible clock chip */ 109 ATARIHW_DECLARE(MSTE_CLK); /* Mega ST(E) clock chip */ 110 /* supporting hardware */ 111 ATARIHW_DECLARE(SCU); /* System Control Unit */ 112 ATARIHW_DECLARE(BLITTER); /* Blitter */ 113 ATARIHW_DECLARE(VME); /* VME Bus */ 114 ATARIHW_DECLARE(DSP56K); /* DSP56k processor in Falcon */ 115 }; 116 117 extern struct atari_hw_present atari_hw_present; 118 119 120 /* Reading the MFP port register gives a machine independent delay, since the 121 * MFP always has a 8 MHz clock. This avoids problems with the varying length 122 * of nops on various machines. Somebody claimed that the tstb takes 600 ns. 123 */ 124 #define MFPDELAY() \ 125 __asm__ __volatile__ ( "tstb %0" : : "m" (st_mfp.par_dt_reg) : "cc" ); 126 127 /* Do cache push/invalidate for DMA read/write. This function obeys the 128 * snooping on some machines (Medusa) and processors: The Medusa itself can 129 * snoop, but only the '040 can source data from its cache to DMA writes i.e., 130 * reads from memory). Both '040 and '060 invalidate cache entries on snooped 131 * DMA reads (i.e., writes to memory). 132 */ 133 134 135 #define atari_readb raw_inb 136 #define atari_writeb raw_outb 137 138 #define atari_inb_p raw_inb 139 #define atari_outb_p raw_outb 140 141 142 143 #include <linux/mm.h> 144 #include <asm/cacheflush.h> 145 146 static inline void dma_cache_maintenance( unsigned long paddr, 147 unsigned long len, 148 int writeflag ) 149 150 { 151 if (writeflag) { 152 if (!MACH_IS_MEDUSA || CPU_IS_060) 153 cache_push( paddr, len ); 154 } 155 else { 156 if (!MACH_IS_MEDUSA) 157 cache_clear( paddr, len ); 158 } 159 } 160 161 162 /* 163 ** Shifter 164 */ 165 #define ST_LOW 0 166 #define ST_MID 1 167 #define ST_HIGH 2 168 #define TT_LOW 7 169 #define TT_MID 4 170 #define TT_HIGH 6 171 172 #define SHF_BAS (0xffff8200) 173 struct SHIFTER 174 { 175 u_char pad1; 176 u_char bas_hi; 177 u_char pad2; 178 u_char bas_md; 179 u_char pad3; 180 u_char volatile vcounthi; 181 u_char pad4; 182 u_char volatile vcountmid; 183 u_char pad5; 184 u_char volatile vcountlow; 185 u_char volatile syncmode; 186 u_char pad6; 187 u_char pad7; 188 u_char bas_lo; 189 }; 190 # define shifter ((*(volatile struct SHIFTER *)SHF_BAS)) 191 192 #define SHF_FBAS (0xffff820e) 193 struct SHIFTER_F030 194 { 195 u_short off_next; 196 u_short scn_width; 197 }; 198 # define shifter_f030 ((*(volatile struct SHIFTER_F030 *)SHF_FBAS)) 199 200 201 #define SHF_TBAS (0xffff8200) 202 struct SHIFTER_TT { 203 u_char char_dummy0; 204 u_char bas_hi; /* video mem base addr, high and mid byte */ 205 u_char char_dummy1; 206 u_char bas_md; 207 u_char char_dummy2; 208 u_char vcount_hi; /* pointer to currently displayed byte */ 209 u_char char_dummy3; 210 u_char vcount_md; 211 u_char char_dummy4; 212 u_char vcount_lo; 213 u_short st_sync; /* ST compatible sync mode register, unused */ 214 u_char char_dummy5; 215 u_char bas_lo; /* video mem addr, low byte */ 216 u_char char_dummy6[2+3*16]; 217 /* $ffff8240: */ 218 u_short color_reg[16]; /* 16 color registers */ 219 u_char st_shiftmode; /* ST compatible shift mode register, unused */ 220 u_char char_dummy7; 221 u_short tt_shiftmode; /* TT shift mode register */ 222 223 224 }; 225 #define shifter_tt ((*(volatile struct SHIFTER_TT *)SHF_TBAS)) 226 227 /* values for shifter_tt->tt_shiftmode */ 228 #define TT_SHIFTER_STLOW 0x0000 229 #define TT_SHIFTER_STMID 0x0100 230 #define TT_SHIFTER_STHIGH 0x0200 231 #define TT_SHIFTER_TTLOW 0x0700 232 #define TT_SHIFTER_TTMID 0x0400 233 #define TT_SHIFTER_TTHIGH 0x0600 234 #define TT_SHIFTER_MODEMASK 0x0700 235 #define TT_SHIFTER_NUMMODE 0x0008 236 #define TT_SHIFTER_PALETTE_MASK 0x000f 237 #define TT_SHIFTER_GRAYMODE 0x1000 238 239 /* 256 TT palette registers */ 240 #define TT_PALETTE_BASE (0xffff8400) 241 #define tt_palette ((volatile u_short *)TT_PALETTE_BASE) 242 243 #define TT_PALETTE_RED_MASK 0x0f00 244 #define TT_PALETTE_GREEN_MASK 0x00f0 245 #define TT_PALETTE_BLUE_MASK 0x000f 246 247 /* 248 ** Falcon030 VIDEL Video Controller 249 ** for description see File 'linux\tools\atari\hardware.txt 250 */ 251 #define f030_col ((u_long *) 0xffff9800) 252 #define f030_xreg ((u_short*) 0xffff8282) 253 #define f030_yreg ((u_short*) 0xffff82a2) 254 #define f030_creg ((u_short*) 0xffff82c0) 255 #define f030_sreg ((u_short*) 0xffff8260) 256 #define f030_mreg ((u_short*) 0xffff820a) 257 #define f030_linewidth ((u_short*) 0xffff820e) 258 #define f030_hscroll ((u_char*) 0xffff8265) 259 260 #define VIDEL_BAS (0xffff8260) 261 struct VIDEL { 262 u_short st_shift; 263 u_short pad1; 264 u_char xoffset_s; 265 u_char xoffset; 266 u_short f_shift; 267 u_char pad2[0x1a]; 268 u_short hht; 269 u_short hbb; 270 u_short hbe; 271 u_short hdb; 272 u_short hde; 273 u_short hss; 274 u_char pad3[0x14]; 275 u_short vft; 276 u_short vbb; 277 u_short vbe; 278 u_short vdb; 279 u_short vde; 280 u_short vss; 281 u_char pad4[0x12]; 282 u_short control; 283 u_short mode; 284 }; 285 #define videl ((*(volatile struct VIDEL *)VIDEL_BAS)) 286 287 /* 288 ** DMA/WD1772 Disk Controller 289 */ 290 291 #define FWD_BAS (0xffff8604) 292 struct DMA_WD 293 { 294 u_short fdc_acces_seccount; 295 u_short dma_mode_status; 296 u_char dma_vhi; /* Some extended ST-DMAs can handle 32 bit addresses */ 297 u_char dma_hi; 298 u_char char_dummy2; 299 u_char dma_md; 300 u_char char_dummy3; 301 u_char dma_lo; 302 u_short fdc_speed; 303 }; 304 # define dma_wd ((*(volatile struct DMA_WD *)FWD_BAS)) 305 /* alias */ 306 #define st_dma dma_wd 307 /* The two highest bytes of an extended DMA as a short; this is a must 308 * for the Medusa. 309 */ 310 #define st_dma_ext_dmahi (*((volatile unsigned short *)0xffff8608)) 311 312 /* 313 ** YM2149 Sound Chip 314 ** access in bytes 315 */ 316 317 #define YM_BAS (0xffff8800) 318 struct SOUND_YM 319 { 320 u_char rd_data_reg_sel; 321 u_char char_dummy1; 322 u_char wd_data; 323 }; 324 #define sound_ym ((*(volatile struct SOUND_YM *)YM_BAS)) 325 326 /* TT SCSI DMA */ 327 328 #define TT_SCSI_DMA_BAS (0xffff8700) 329 struct TT_DMA { 330 u_char char_dummy0; 331 u_char dma_addr_hi; 332 u_char char_dummy1; 333 u_char dma_addr_hmd; 334 u_char char_dummy2; 335 u_char dma_addr_lmd; 336 u_char char_dummy3; 337 u_char dma_addr_lo; 338 u_char char_dummy4; 339 u_char dma_cnt_hi; 340 u_char char_dummy5; 341 u_char dma_cnt_hmd; 342 u_char char_dummy6; 343 u_char dma_cnt_lmd; 344 u_char char_dummy7; 345 u_char dma_cnt_lo; 346 u_long dma_restdata; 347 u_short dma_ctrl; 348 }; 349 #define tt_scsi_dma ((*(volatile struct TT_DMA *)TT_SCSI_DMA_BAS)) 350 351 /* TT SCSI Controller 5380 */ 352 353 #define TT_5380_BAS (0xffff8781) 354 struct TT_5380 { 355 u_char scsi_data; 356 u_char char_dummy1; 357 u_char scsi_icr; 358 u_char char_dummy2; 359 u_char scsi_mode; 360 u_char char_dummy3; 361 u_char scsi_tcr; 362 u_char char_dummy4; 363 u_char scsi_idstat; 364 u_char char_dummy5; 365 u_char scsi_dmastat; 366 u_char char_dummy6; 367 u_char scsi_targrcv; 368 u_char char_dummy7; 369 u_char scsi_inircv; 370 }; 371 #define tt_scsi ((*(volatile struct TT_5380 *)TT_5380_BAS)) 372 #define tt_scsi_regp ((volatile char *)TT_5380_BAS) 373 374 375 /* 376 ** Falcon DMA Sound Subsystem 377 */ 378 379 #define MATRIX_BASE (0xffff8930) 380 struct MATRIX 381 { 382 u_short source; 383 u_short destination; 384 u_char external_frequency_divider; 385 u_char internal_frequency_divider; 386 }; 387 #define falcon_matrix (*(volatile struct MATRIX *)MATRIX_BASE) 388 389 #define CODEC_BASE (0xffff8936) 390 struct CODEC 391 { 392 u_char tracks; 393 u_char input_source; 394 #define CODEC_SOURCE_ADC 1 395 #define CODEC_SOURCE_MATRIX 2 396 u_char adc_source; 397 #define ADC_SOURCE_RIGHT_PSG 1 398 #define ADC_SOURCE_LEFT_PSG 2 399 u_char gain; 400 #define CODEC_GAIN_RIGHT 0x0f 401 #define CODEC_GAIN_LEFT 0xf0 402 u_char attenuation; 403 #define CODEC_ATTENUATION_RIGHT 0x0f 404 #define CODEC_ATTENUATION_LEFT 0xf0 405 u_char unused1; 406 u_char status; 407 #define CODEC_OVERFLOW_RIGHT 1 408 #define CODEC_OVERFLOW_LEFT 2 409 u_char unused2, unused3, unused4, unused5; 410 u_char gpio_directions; 411 #define CODEC_GPIO_IN 0 412 #define CODEC_GPIO_OUT 1 413 u_char unused6; 414 u_char gpio_data; 415 }; 416 #define falcon_codec (*(volatile struct CODEC *)CODEC_BASE) 417 418 /* 419 ** Falcon Blitter 420 */ 421 422 #define BLT_BAS (0xffff8a00) 423 424 struct BLITTER 425 { 426 u_short halftone[16]; 427 u_short src_x_inc; 428 u_short src_y_inc; 429 u_long src_address; 430 u_short endmask1; 431 u_short endmask2; 432 u_short endmask3; 433 u_short dst_x_inc; 434 u_short dst_y_inc; 435 u_long dst_address; 436 u_short wd_per_line; 437 u_short ln_per_bb; 438 u_short hlf_op_reg; 439 u_short log_op_reg; 440 u_short lin_nm_reg; 441 u_short skew_reg; 442 }; 443 # define blitter ((*(volatile struct BLITTER *)BLT_BAS)) 444 445 446 /* 447 ** SCC Z8530 448 */ 449 450 #define SCC_BAS (0xffff8c81) 451 struct SCC 452 { 453 u_char cha_a_ctrl; 454 u_char char_dummy1; 455 u_char cha_a_data; 456 u_char char_dummy2; 457 u_char cha_b_ctrl; 458 u_char char_dummy3; 459 u_char cha_b_data; 460 }; 461 # define atari_scc ((*(volatile struct SCC*)SCC_BAS)) 462 463 /* The ESCC (Z85230) in an Atari ST. The channels are reversed! */ 464 # define st_escc ((*(volatile struct SCC*)0xfffffa31)) 465 # define st_escc_dsr ((*(volatile char *)0xfffffa39)) 466 467 /* TT SCC DMA Controller (same chip as SCSI DMA) */ 468 469 #define TT_SCC_DMA_BAS (0xffff8c00) 470 #define tt_scc_dma ((*(volatile struct TT_DMA *)TT_SCC_DMA_BAS)) 471 472 /* 473 ** VIDEL Palette Register 474 */ 475 476 #define FPL_BAS (0xffff9800) 477 struct VIDEL_PALETTE 478 { 479 u_long reg[256]; 480 }; 481 # define videl_palette ((*(volatile struct VIDEL_PALETTE*)FPL_BAS)) 482 483 484 /* 485 ** Falcon DSP Host Interface 486 */ 487 488 #define DSP56K_HOST_INTERFACE_BASE (0xffffa200) 489 struct DSP56K_HOST_INTERFACE { 490 u_char icr; 491 #define DSP56K_ICR_RREQ 0x01 492 #define DSP56K_ICR_TREQ 0x02 493 #define DSP56K_ICR_HF0 0x08 494 #define DSP56K_ICR_HF1 0x10 495 #define DSP56K_ICR_HM0 0x20 496 #define DSP56K_ICR_HM1 0x40 497 #define DSP56K_ICR_INIT 0x80 498 499 u_char cvr; 500 #define DSP56K_CVR_HV_MASK 0x1f 501 #define DSP56K_CVR_HC 0x80 502 503 u_char isr; 504 #define DSP56K_ISR_RXDF 0x01 505 #define DSP56K_ISR_TXDE 0x02 506 #define DSP56K_ISR_TRDY 0x04 507 #define DSP56K_ISR_HF2 0x08 508 #define DSP56K_ISR_HF3 0x10 509 #define DSP56K_ISR_DMA 0x40 510 #define DSP56K_ISR_HREQ 0x80 511 512 u_char ivr; 513 514 union { 515 u_char b[4]; 516 u_short w[2]; 517 u_long l; 518 } data; 519 }; 520 #define dsp56k_host_interface ((*(volatile struct DSP56K_HOST_INTERFACE *)DSP56K_HOST_INTERFACE_BASE)) 521 522 /* 523 ** MFP 68901 524 */ 525 526 #define MFP_BAS (0xfffffa01) 527 struct MFP 528 { 529 u_char par_dt_reg; 530 u_char char_dummy1; 531 u_char active_edge; 532 u_char char_dummy2; 533 u_char data_dir; 534 u_char char_dummy3; 535 u_char int_en_a; 536 u_char char_dummy4; 537 u_char int_en_b; 538 u_char char_dummy5; 539 u_char int_pn_a; 540 u_char char_dummy6; 541 u_char int_pn_b; 542 u_char char_dummy7; 543 u_char int_sv_a; 544 u_char char_dummy8; 545 u_char int_sv_b; 546 u_char char_dummy9; 547 u_char int_mk_a; 548 u_char char_dummy10; 549 u_char int_mk_b; 550 u_char char_dummy11; 551 u_char vec_adr; 552 u_char char_dummy12; 553 u_char tim_ct_a; 554 u_char char_dummy13; 555 u_char tim_ct_b; 556 u_char char_dummy14; 557 u_char tim_ct_cd; 558 u_char char_dummy15; 559 u_char tim_dt_a; 560 u_char char_dummy16; 561 u_char tim_dt_b; 562 u_char char_dummy17; 563 u_char tim_dt_c; 564 u_char char_dummy18; 565 u_char tim_dt_d; 566 u_char char_dummy19; 567 u_char sync_char; 568 u_char char_dummy20; 569 u_char usart_ctr; 570 u_char char_dummy21; 571 u_char rcv_stat; 572 u_char char_dummy22; 573 u_char trn_stat; 574 u_char char_dummy23; 575 u_char usart_dta; 576 }; 577 # define st_mfp ((*(volatile struct MFP*)MFP_BAS)) 578 579 /* TT's second MFP */ 580 581 #define TT_MFP_BAS (0xfffffa81) 582 # define tt_mfp ((*(volatile struct MFP*)TT_MFP_BAS)) 583 584 585 /* TT System Control Unit */ 586 587 #define TT_SCU_BAS (0xffff8e01) 588 struct TT_SCU { 589 u_char sys_mask; 590 u_char char_dummy1; 591 u_char sys_stat; 592 u_char char_dummy2; 593 u_char softint; 594 u_char char_dummy3; 595 u_char vmeint; 596 u_char char_dummy4; 597 u_char gp_reg1; 598 u_char char_dummy5; 599 u_char gp_reg2; 600 u_char char_dummy6; 601 u_char vme_mask; 602 u_char char_dummy7; 603 u_char vme_stat; 604 }; 605 #define tt_scu ((*(volatile struct TT_SCU *)TT_SCU_BAS)) 606 607 /* TT real time clock */ 608 609 #define TT_RTC_BAS (0xffff8961) 610 struct TT_RTC { 611 u_char regsel; 612 u_char dummy; 613 u_char data; 614 }; 615 #define tt_rtc ((*(volatile struct TT_RTC *)TT_RTC_BAS)) 616 617 618 /* 619 ** ACIA 6850 620 */ 621 /* constants for the ACIA registers */ 622 623 /* baudrate selection and reset (Baudrate = clock/factor) */ 624 #define ACIA_DIV1 0 625 #define ACIA_DIV16 1 626 #define ACIA_DIV64 2 627 #define ACIA_RESET 3 628 629 /* character format */ 630 #define ACIA_D7E2S (0<<2) /* 7 data, even parity, 2 stop */ 631 #define ACIA_D7O2S (1<<2) /* 7 data, odd parity, 2 stop */ 632 #define ACIA_D7E1S (2<<2) /* 7 data, even parity, 1 stop */ 633 #define ACIA_D7O1S (3<<2) /* 7 data, odd parity, 1 stop */ 634 #define ACIA_D8N2S (4<<2) /* 8 data, no parity, 2 stop */ 635 #define ACIA_D8N1S (5<<2) /* 8 data, no parity, 1 stop */ 636 #define ACIA_D8E1S (6<<2) /* 8 data, even parity, 1 stop */ 637 #define ACIA_D8O1S (7<<2) /* 8 data, odd parity, 1 stop */ 638 639 /* transmit control */ 640 #define ACIA_RLTID (0<<5) /* RTS low, TxINT disabled */ 641 #define ACIA_RLTIE (1<<5) /* RTS low, TxINT enabled */ 642 #define ACIA_RHTID (2<<5) /* RTS high, TxINT disabled */ 643 #define ACIA_RLTIDSB (3<<5) /* RTS low, TxINT disabled, send break */ 644 645 /* receive control */ 646 #define ACIA_RID (0<<7) /* RxINT disabled */ 647 #define ACIA_RIE (1<<7) /* RxINT enabled */ 648 649 /* status fields of the ACIA */ 650 #define ACIA_RDRF 1 /* Receive Data Register Full */ 651 #define ACIA_TDRE (1<<1) /* Transmit Data Register Empty */ 652 #define ACIA_DCD (1<<2) /* Data Carrier Detect */ 653 #define ACIA_CTS (1<<3) /* Clear To Send */ 654 #define ACIA_FE (1<<4) /* Framing Error */ 655 #define ACIA_OVRN (1<<5) /* Receiver Overrun */ 656 #define ACIA_PE (1<<6) /* Parity Error */ 657 #define ACIA_IRQ (1<<7) /* Interrupt Request */ 658 659 #define ACIA_BAS (0xfffffc00) 660 struct ACIA 661 { 662 u_char key_ctrl; 663 u_char char_dummy1; 664 u_char key_data; 665 u_char char_dummy2; 666 u_char mid_ctrl; 667 u_char char_dummy3; 668 u_char mid_data; 669 }; 670 # define acia ((*(volatile struct ACIA*)ACIA_BAS)) 671 672 #define TT_DMASND_BAS (0xffff8900) 673 struct TT_DMASND { 674 u_char int_ctrl; /* Falcon: Interrupt control */ 675 u_char ctrl; 676 u_char pad2; 677 u_char bas_hi; 678 u_char pad3; 679 u_char bas_mid; 680 u_char pad4; 681 u_char bas_low; 682 u_char pad5; 683 u_char addr_hi; 684 u_char pad6; 685 u_char addr_mid; 686 u_char pad7; 687 u_char addr_low; 688 u_char pad8; 689 u_char end_hi; 690 u_char pad9; 691 u_char end_mid; 692 u_char pad10; 693 u_char end_low; 694 u_char pad11[12]; 695 u_char track_select; /* Falcon */ 696 u_char mode; 697 u_char pad12[14]; 698 /* Falcon only: */ 699 u_short cbar_src; 700 u_short cbar_dst; 701 u_char ext_div; 702 u_char int_div; 703 u_char rec_track_select; 704 u_char dac_src; 705 u_char adc_src; 706 u_char input_gain; 707 u_short output_atten; 708 }; 709 # define tt_dmasnd ((*(volatile struct TT_DMASND *)TT_DMASND_BAS)) 710 711 #define DMASND_MFP_INT_REPLAY 0x01 712 #define DMASND_MFP_INT_RECORD 0x02 713 #define DMASND_TIMERA_INT_REPLAY 0x04 714 #define DMASND_TIMERA_INT_RECORD 0x08 715 716 #define DMASND_CTRL_OFF 0x00 717 #define DMASND_CTRL_ON 0x01 718 #define DMASND_CTRL_REPEAT 0x02 719 #define DMASND_CTRL_RECORD_ON 0x10 720 #define DMASND_CTRL_RECORD_OFF 0x00 721 #define DMASND_CTRL_RECORD_REPEAT 0x20 722 #define DMASND_CTRL_SELECT_REPLAY 0x00 723 #define DMASND_CTRL_SELECT_RECORD 0x80 724 #define DMASND_MODE_MONO 0x80 725 #define DMASND_MODE_STEREO 0x00 726 #define DMASND_MODE_8BIT 0x00 727 #define DMASND_MODE_16BIT 0x40 /* Falcon only */ 728 #define DMASND_MODE_6KHZ 0x00 /* Falcon: mute */ 729 #define DMASND_MODE_12KHZ 0x01 730 #define DMASND_MODE_25KHZ 0x02 731 #define DMASND_MODE_50KHZ 0x03 732 733 734 #define DMASNDSetBase(bufstart) \ 735 do { \ 736 tt_dmasnd.bas_hi = (unsigned char)(((bufstart) & 0xff0000) >> 16); \ 737 tt_dmasnd.bas_mid = (unsigned char)(((bufstart) & 0x00ff00) >> 8); \ 738 tt_dmasnd.bas_low = (unsigned char) ((bufstart) & 0x0000ff); \ 739 } while( 0 ) 740 741 #define DMASNDGetAdr() ((tt_dmasnd.addr_hi << 16) + \ 742 (tt_dmasnd.addr_mid << 8) + \ 743 (tt_dmasnd.addr_low)) 744 745 #define DMASNDSetEnd(bufend) \ 746 do { \ 747 tt_dmasnd.end_hi = (unsigned char)(((bufend) & 0xff0000) >> 16); \ 748 tt_dmasnd.end_mid = (unsigned char)(((bufend) & 0x00ff00) >> 8); \ 749 tt_dmasnd.end_low = (unsigned char) ((bufend) & 0x0000ff); \ 750 } while( 0 ) 751 752 753 #define TT_MICROWIRE_BAS (0xffff8922) 754 struct TT_MICROWIRE { 755 u_short data; 756 u_short mask; 757 }; 758 # define tt_microwire ((*(volatile struct TT_MICROWIRE *)TT_MICROWIRE_BAS)) 759 760 #define MW_LM1992_ADDR 0x0400 761 762 #define MW_LM1992_VOLUME(dB) \ 763 (0x0c0 | ((dB) < -80 ? 0 : (dB) > 0 ? 40 : (((dB) + 80) / 2))) 764 #define MW_LM1992_BALLEFT(dB) \ 765 (0x140 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2))) 766 #define MW_LM1992_BALRIGHT(dB) \ 767 (0x100 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2))) 768 #define MW_LM1992_TREBLE(dB) \ 769 (0x080 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6))) 770 #define MW_LM1992_BASS(dB) \ 771 (0x040 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6))) 772 773 #define MW_LM1992_PSG_LOW 0x000 774 #define MW_LM1992_PSG_HIGH 0x001 775 #define MW_LM1992_PSG_OFF 0x002 776 777 #define MSTE_RTC_BAS (0xfffffc21) 778 779 struct MSTE_RTC { 780 u_char sec_ones; 781 u_char dummy1; 782 u_char sec_tens; 783 u_char dummy2; 784 u_char min_ones; 785 u_char dummy3; 786 u_char min_tens; 787 u_char dummy4; 788 u_char hr_ones; 789 u_char dummy5; 790 u_char hr_tens; 791 u_char dummy6; 792 u_char weekday; 793 u_char dummy7; 794 u_char day_ones; 795 u_char dummy8; 796 u_char day_tens; 797 u_char dummy9; 798 u_char mon_ones; 799 u_char dummy10; 800 u_char mon_tens; 801 u_char dummy11; 802 u_char year_ones; 803 u_char dummy12; 804 u_char year_tens; 805 u_char dummy13; 806 u_char mode; 807 u_char dummy14; 808 u_char test; 809 u_char dummy15; 810 u_char reset; 811 }; 812 813 #define mste_rtc ((*(volatile struct MSTE_RTC *)MSTE_RTC_BAS)) 814 815 /* 816 ** EtherNAT add-on card for Falcon - combined ethernet and USB adapter 817 */ 818 819 #define ATARI_ETHERNAT_PHYS_ADDR 0x80000000 820 821 #endif /* linux/atarihw.h */ 822 823