1 /* 2 ** linux/atarihw.h -- This header defines some macros and pointers for 3 ** the various Atari custom hardware registers. 4 ** 5 ** Copyright 1994 by Björn Brauel 6 ** 7 ** 5/1/94 Roman Hodek: 8 ** Added definitions for TT specific chips. 9 ** 10 ** 1996-09-13 lars brinkhoff <f93labr@dd.chalmers.se>: 11 ** Finally added definitions for the matrix/codec and the DSP56001 host 12 ** interface. 13 ** 14 ** This file is subject to the terms and conditions of the GNU General Public 15 ** License. See the file COPYING in the main directory of this archive 16 ** for more details. 17 ** 18 */ 19 20 #ifndef _LINUX_ATARIHW_H_ 21 #define _LINUX_ATARIHW_H_ 22 23 #include <linux/types.h> 24 #include <asm/bootinfo-atari.h> 25 #include <asm/raw_io.h> 26 #include <asm/kmap.h> 27 28 extern u_long atari_mch_cookie; 29 extern u_long atari_mch_type; 30 extern u_long atari_switches; 31 extern int atari_rtc_year_offset; 32 extern int atari_dont_touch_floppy_select; 33 34 extern int atari_SCC_reset_done; 35 36 /* convenience macros for testing machine type */ 37 #define MACH_IS_ST ((atari_mch_cookie >> 16) == ATARI_MCH_ST) 38 #define MACH_IS_STE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \ 39 (atari_mch_cookie & 0xffff) == 0) 40 #define MACH_IS_MSTE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \ 41 (atari_mch_cookie & 0xffff) == 0x10) 42 #define MACH_IS_TT ((atari_mch_cookie >> 16) == ATARI_MCH_TT) 43 #define MACH_IS_FALCON ((atari_mch_cookie >> 16) == ATARI_MCH_FALCON) 44 #define MACH_IS_MEDUSA (atari_mch_type == ATARI_MACH_MEDUSA) 45 #define MACH_IS_AB40 (atari_mch_type == ATARI_MACH_AB40) 46 47 /* values for atari_switches */ 48 #define ATARI_SWITCH_IKBD 0x01 49 #define ATARI_SWITCH_MIDI 0x02 50 #define ATARI_SWITCH_SND6 0x04 51 #define ATARI_SWITCH_SND7 0x08 52 #define ATARI_SWITCH_OVSC_SHIFT 16 53 #define ATARI_SWITCH_OVSC_IKBD (ATARI_SWITCH_IKBD << ATARI_SWITCH_OVSC_SHIFT) 54 #define ATARI_SWITCH_OVSC_MIDI (ATARI_SWITCH_MIDI << ATARI_SWITCH_OVSC_SHIFT) 55 #define ATARI_SWITCH_OVSC_SND6 (ATARI_SWITCH_SND6 << ATARI_SWITCH_OVSC_SHIFT) 56 #define ATARI_SWITCH_OVSC_SND7 (ATARI_SWITCH_SND7 << ATARI_SWITCH_OVSC_SHIFT) 57 #define ATARI_SWITCH_OVSC_MASK 0xffff0000 58 59 /* 60 * Define several Hardware-Chips for indication so that for the ATARI we do 61 * no longer decide whether it is a Falcon or other machine . It's just 62 * important what hardware the machine uses 63 */ 64 65 /* ++roman 08/08/95: rewritten from ORing constants to a C bitfield */ 66 67 #define ATARIHW_DECLARE(name) unsigned name : 1 68 #define ATARIHW_SET(name) (atari_hw_present.name = 1) 69 #define ATARIHW_PRESENT(name) (atari_hw_present.name) 70 71 struct atari_hw_present { 72 /* video hardware */ 73 ATARIHW_DECLARE(STND_SHIFTER); /* ST-Shifter - no base low ! */ 74 ATARIHW_DECLARE(EXTD_SHIFTER); /* STe-Shifter - 24 bit address */ 75 ATARIHW_DECLARE(TT_SHIFTER); /* TT-Shifter */ 76 ATARIHW_DECLARE(VIDEL_SHIFTER); /* Falcon-Shifter */ 77 /* sound hardware */ 78 ATARIHW_DECLARE(YM_2149); /* Yamaha YM 2149 */ 79 ATARIHW_DECLARE(PCM_8BIT); /* PCM-Sound in STe-ATARI */ 80 ATARIHW_DECLARE(CODEC); /* CODEC Sound (Falcon) */ 81 /* disk storage interfaces */ 82 ATARIHW_DECLARE(TT_SCSI); /* Directly mapped NCR5380 */ 83 ATARIHW_DECLARE(ST_SCSI); /* NCR5380 via ST-DMA (Falcon) */ 84 ATARIHW_DECLARE(ACSI); /* Standard ACSI like in STs */ 85 ATARIHW_DECLARE(IDE); /* IDE Interface */ 86 ATARIHW_DECLARE(FDCSPEED); /* 8/16 MHz switch for FDC */ 87 /* other I/O hardware */ 88 ATARIHW_DECLARE(ST_MFP); /* The ST-MFP (there should be no Atari 89 without it... but who knows?) */ 90 ATARIHW_DECLARE(TT_MFP); /* 2nd MFP */ 91 ATARIHW_DECLARE(SCC); /* Serial Communications Contr. */ 92 ATARIHW_DECLARE(ST_ESCC); /* SCC Z83230 in an ST */ 93 ATARIHW_DECLARE(ANALOG_JOY); /* Paddle Interface for STe 94 and Falcon */ 95 ATARIHW_DECLARE(MICROWIRE); /* Microwire Interface */ 96 /* DMA */ 97 ATARIHW_DECLARE(STND_DMA); /* 24 Bit limited ST-DMA */ 98 ATARIHW_DECLARE(EXTD_DMA); /* 32 Bit ST-DMA */ 99 ATARIHW_DECLARE(SCSI_DMA); /* DMA for the NCR5380 */ 100 ATARIHW_DECLARE(SCC_DMA); /* DMA for the SCC */ 101 /* real time clocks */ 102 ATARIHW_DECLARE(TT_CLK); /* TT compatible clock chip */ 103 ATARIHW_DECLARE(MSTE_CLK); /* Mega ST(E) clock chip */ 104 /* supporting hardware */ 105 ATARIHW_DECLARE(SCU); /* System Control Unit */ 106 ATARIHW_DECLARE(BLITTER); /* Blitter */ 107 ATARIHW_DECLARE(VME); /* VME Bus */ 108 ATARIHW_DECLARE(DSP56K); /* DSP56k processor in Falcon */ 109 }; 110 111 extern struct atari_hw_present atari_hw_present; 112 113 114 /* Reading the MFP port register gives a machine independent delay, since the 115 * MFP always has a 8 MHz clock. This avoids problems with the varying length 116 * of nops on various machines. Somebody claimed that the tstb takes 600 ns. 117 */ 118 #define MFPDELAY() \ 119 __asm__ __volatile__ ( "tstb %0" : : "m" (st_mfp.par_dt_reg) : "cc" ); 120 121 /* Do cache push/invalidate for DMA read/write. This function obeys the 122 * snooping on some machines (Medusa) and processors: The Medusa itself can 123 * snoop, but only the '040 can source data from its cache to DMA writes i.e., 124 * reads from memory). Both '040 and '060 invalidate cache entries on snooped 125 * DMA reads (i.e., writes to memory). 126 */ 127 128 129 #define atari_readb raw_inb 130 #define atari_writeb raw_outb 131 132 #define atari_inb_p raw_inb 133 #define atari_outb_p raw_outb 134 135 136 137 #include <linux/mm.h> 138 #include <asm/cacheflush.h> 139 140 static inline void dma_cache_maintenance( unsigned long paddr, 141 unsigned long len, 142 int writeflag ) 143 144 { 145 if (writeflag) { 146 if (!MACH_IS_MEDUSA || CPU_IS_060) 147 cache_push( paddr, len ); 148 } 149 else { 150 if (!MACH_IS_MEDUSA) 151 cache_clear( paddr, len ); 152 } 153 } 154 155 156 /* 157 ** Shifter 158 */ 159 #define ST_LOW 0 160 #define ST_MID 1 161 #define ST_HIGH 2 162 #define TT_LOW 7 163 #define TT_MID 4 164 #define TT_HIGH 6 165 166 #define SHF_BAS (0xffff8200) 167 struct SHIFTER 168 { 169 u_char pad1; 170 u_char bas_hi; 171 u_char pad2; 172 u_char bas_md; 173 u_char pad3; 174 u_char volatile vcounthi; 175 u_char pad4; 176 u_char volatile vcountmid; 177 u_char pad5; 178 u_char volatile vcountlow; 179 u_char volatile syncmode; 180 u_char pad6; 181 u_char pad7; 182 u_char bas_lo; 183 }; 184 # define shifter ((*(volatile struct SHIFTER *)SHF_BAS)) 185 186 #define SHF_FBAS (0xffff820e) 187 struct SHIFTER_F030 188 { 189 u_short off_next; 190 u_short scn_width; 191 }; 192 # define shifter_f030 ((*(volatile struct SHIFTER_F030 *)SHF_FBAS)) 193 194 195 #define SHF_TBAS (0xffff8200) 196 struct SHIFTER_TT { 197 u_char char_dummy0; 198 u_char bas_hi; /* video mem base addr, high and mid byte */ 199 u_char char_dummy1; 200 u_char bas_md; 201 u_char char_dummy2; 202 u_char vcount_hi; /* pointer to currently displayed byte */ 203 u_char char_dummy3; 204 u_char vcount_md; 205 u_char char_dummy4; 206 u_char vcount_lo; 207 u_short st_sync; /* ST compatible sync mode register, unused */ 208 u_char char_dummy5; 209 u_char bas_lo; /* video mem addr, low byte */ 210 u_char char_dummy6[2+3*16]; 211 /* $ffff8240: */ 212 u_short color_reg[16]; /* 16 color registers */ 213 u_char st_shiftmode; /* ST compatible shift mode register, unused */ 214 u_char char_dummy7; 215 u_short tt_shiftmode; /* TT shift mode register */ 216 217 218 }; 219 #define shifter_tt ((*(volatile struct SHIFTER_TT *)SHF_TBAS)) 220 221 /* values for shifter_tt->tt_shiftmode */ 222 #define TT_SHIFTER_STLOW 0x0000 223 #define TT_SHIFTER_STMID 0x0100 224 #define TT_SHIFTER_STHIGH 0x0200 225 #define TT_SHIFTER_TTLOW 0x0700 226 #define TT_SHIFTER_TTMID 0x0400 227 #define TT_SHIFTER_TTHIGH 0x0600 228 #define TT_SHIFTER_MODEMASK 0x0700 229 #define TT_SHIFTER_NUMMODE 0x0008 230 #define TT_SHIFTER_PALETTE_MASK 0x000f 231 #define TT_SHIFTER_GRAYMODE 0x1000 232 233 /* 256 TT palette registers */ 234 #define TT_PALETTE_BASE (0xffff8400) 235 #define tt_palette ((volatile u_short *)TT_PALETTE_BASE) 236 237 #define TT_PALETTE_RED_MASK 0x0f00 238 #define TT_PALETTE_GREEN_MASK 0x00f0 239 #define TT_PALETTE_BLUE_MASK 0x000f 240 241 /* 242 ** Falcon030 VIDEL Video Controller 243 ** for description see File 'linux\tools\atari\hardware.txt 244 */ 245 #define f030_col ((u_long *) 0xffff9800) 246 #define f030_xreg ((u_short*) 0xffff8282) 247 #define f030_yreg ((u_short*) 0xffff82a2) 248 #define f030_creg ((u_short*) 0xffff82c0) 249 #define f030_sreg ((u_short*) 0xffff8260) 250 #define f030_mreg ((u_short*) 0xffff820a) 251 #define f030_linewidth ((u_short*) 0xffff820e) 252 #define f030_hscroll ((u_char*) 0xffff8265) 253 254 #define VIDEL_BAS (0xffff8260) 255 struct VIDEL { 256 u_short st_shift; 257 u_short pad1; 258 u_char xoffset_s; 259 u_char xoffset; 260 u_short f_shift; 261 u_char pad2[0x1a]; 262 u_short hht; 263 u_short hbb; 264 u_short hbe; 265 u_short hdb; 266 u_short hde; 267 u_short hss; 268 u_char pad3[0x14]; 269 u_short vft; 270 u_short vbb; 271 u_short vbe; 272 u_short vdb; 273 u_short vde; 274 u_short vss; 275 u_char pad4[0x12]; 276 u_short control; 277 u_short mode; 278 }; 279 #define videl ((*(volatile struct VIDEL *)VIDEL_BAS)) 280 281 /* 282 ** DMA/WD1772 Disk Controller 283 */ 284 285 #define FWD_BAS (0xffff8604) 286 struct DMA_WD 287 { 288 u_short fdc_acces_seccount; 289 u_short dma_mode_status; 290 u_char dma_vhi; /* Some extended ST-DMAs can handle 32 bit addresses */ 291 u_char dma_hi; 292 u_char char_dummy2; 293 u_char dma_md; 294 u_char char_dummy3; 295 u_char dma_lo; 296 u_short fdc_speed; 297 }; 298 # define dma_wd ((*(volatile struct DMA_WD *)FWD_BAS)) 299 /* alias */ 300 #define st_dma dma_wd 301 /* The two highest bytes of an extended DMA as a short; this is a must 302 * for the Medusa. 303 */ 304 #define st_dma_ext_dmahi (*((volatile unsigned short *)0xffff8608)) 305 306 /* 307 ** YM2149 Sound Chip 308 ** access in bytes 309 */ 310 311 #define YM_BAS (0xffff8800) 312 struct SOUND_YM 313 { 314 u_char rd_data_reg_sel; 315 u_char char_dummy1; 316 u_char wd_data; 317 }; 318 #define sound_ym ((*(volatile struct SOUND_YM *)YM_BAS)) 319 320 /* TT SCSI DMA */ 321 322 #define TT_SCSI_DMA_BAS (0xffff8700) 323 struct TT_DMA { 324 u_char char_dummy0; 325 u_char dma_addr_hi; 326 u_char char_dummy1; 327 u_char dma_addr_hmd; 328 u_char char_dummy2; 329 u_char dma_addr_lmd; 330 u_char char_dummy3; 331 u_char dma_addr_lo; 332 u_char char_dummy4; 333 u_char dma_cnt_hi; 334 u_char char_dummy5; 335 u_char dma_cnt_hmd; 336 u_char char_dummy6; 337 u_char dma_cnt_lmd; 338 u_char char_dummy7; 339 u_char dma_cnt_lo; 340 u_long dma_restdata; 341 u_short dma_ctrl; 342 }; 343 #define tt_scsi_dma ((*(volatile struct TT_DMA *)TT_SCSI_DMA_BAS)) 344 345 /* TT SCSI Controller 5380 */ 346 347 #define TT_5380_BAS (0xffff8781) 348 struct TT_5380 { 349 u_char scsi_data; 350 u_char char_dummy1; 351 u_char scsi_icr; 352 u_char char_dummy2; 353 u_char scsi_mode; 354 u_char char_dummy3; 355 u_char scsi_tcr; 356 u_char char_dummy4; 357 u_char scsi_idstat; 358 u_char char_dummy5; 359 u_char scsi_dmastat; 360 u_char char_dummy6; 361 u_char scsi_targrcv; 362 u_char char_dummy7; 363 u_char scsi_inircv; 364 }; 365 #define tt_scsi ((*(volatile struct TT_5380 *)TT_5380_BAS)) 366 #define tt_scsi_regp ((volatile char *)TT_5380_BAS) 367 368 369 /* 370 ** Falcon DMA Sound Subsystem 371 */ 372 373 #define MATRIX_BASE (0xffff8930) 374 struct MATRIX 375 { 376 u_short source; 377 u_short destination; 378 u_char external_frequency_divider; 379 u_char internal_frequency_divider; 380 }; 381 #define falcon_matrix (*(volatile struct MATRIX *)MATRIX_BASE) 382 383 #define CODEC_BASE (0xffff8936) 384 struct CODEC 385 { 386 u_char tracks; 387 u_char input_source; 388 #define CODEC_SOURCE_ADC 1 389 #define CODEC_SOURCE_MATRIX 2 390 u_char adc_source; 391 #define ADC_SOURCE_RIGHT_PSG 1 392 #define ADC_SOURCE_LEFT_PSG 2 393 u_char gain; 394 #define CODEC_GAIN_RIGHT 0x0f 395 #define CODEC_GAIN_LEFT 0xf0 396 u_char attenuation; 397 #define CODEC_ATTENUATION_RIGHT 0x0f 398 #define CODEC_ATTENUATION_LEFT 0xf0 399 u_char unused1; 400 u_char status; 401 #define CODEC_OVERFLOW_RIGHT 1 402 #define CODEC_OVERFLOW_LEFT 2 403 u_char unused2, unused3, unused4, unused5; 404 u_char gpio_directions; 405 #define CODEC_GPIO_IN 0 406 #define CODEC_GPIO_OUT 1 407 u_char unused6; 408 u_char gpio_data; 409 }; 410 #define falcon_codec (*(volatile struct CODEC *)CODEC_BASE) 411 412 /* 413 ** Falcon Blitter 414 */ 415 416 #define BLT_BAS (0xffff8a00) 417 418 struct BLITTER 419 { 420 u_short halftone[16]; 421 u_short src_x_inc; 422 u_short src_y_inc; 423 u_long src_address; 424 u_short endmask1; 425 u_short endmask2; 426 u_short endmask3; 427 u_short dst_x_inc; 428 u_short dst_y_inc; 429 u_long dst_address; 430 u_short wd_per_line; 431 u_short ln_per_bb; 432 u_short hlf_op_reg; 433 u_short log_op_reg; 434 u_short lin_nm_reg; 435 u_short skew_reg; 436 }; 437 # define blitter ((*(volatile struct BLITTER *)BLT_BAS)) 438 439 440 /* 441 ** SCC Z8530 442 */ 443 444 #define SCC_BAS (0xffff8c81) 445 struct SCC 446 { 447 u_char cha_a_ctrl; 448 u_char char_dummy1; 449 u_char cha_a_data; 450 u_char char_dummy2; 451 u_char cha_b_ctrl; 452 u_char char_dummy3; 453 u_char cha_b_data; 454 }; 455 # define atari_scc ((*(volatile struct SCC*)SCC_BAS)) 456 457 /* The ESCC (Z85230) in an Atari ST. The channels are reversed! */ 458 # define st_escc ((*(volatile struct SCC*)0xfffffa31)) 459 # define st_escc_dsr ((*(volatile char *)0xfffffa39)) 460 461 /* TT SCC DMA Controller (same chip as SCSI DMA) */ 462 463 #define TT_SCC_DMA_BAS (0xffff8c00) 464 #define tt_scc_dma ((*(volatile struct TT_DMA *)TT_SCC_DMA_BAS)) 465 466 /* 467 ** VIDEL Palette Register 468 */ 469 470 #define FPL_BAS (0xffff9800) 471 struct VIDEL_PALETTE 472 { 473 u_long reg[256]; 474 }; 475 # define videl_palette ((*(volatile struct VIDEL_PALETTE*)FPL_BAS)) 476 477 478 /* 479 ** Falcon DSP Host Interface 480 */ 481 482 #define DSP56K_HOST_INTERFACE_BASE (0xffffa200) 483 struct DSP56K_HOST_INTERFACE { 484 u_char icr; 485 #define DSP56K_ICR_RREQ 0x01 486 #define DSP56K_ICR_TREQ 0x02 487 #define DSP56K_ICR_HF0 0x08 488 #define DSP56K_ICR_HF1 0x10 489 #define DSP56K_ICR_HM0 0x20 490 #define DSP56K_ICR_HM1 0x40 491 #define DSP56K_ICR_INIT 0x80 492 493 u_char cvr; 494 #define DSP56K_CVR_HV_MASK 0x1f 495 #define DSP56K_CVR_HC 0x80 496 497 u_char isr; 498 #define DSP56K_ISR_RXDF 0x01 499 #define DSP56K_ISR_TXDE 0x02 500 #define DSP56K_ISR_TRDY 0x04 501 #define DSP56K_ISR_HF2 0x08 502 #define DSP56K_ISR_HF3 0x10 503 #define DSP56K_ISR_DMA 0x40 504 #define DSP56K_ISR_HREQ 0x80 505 506 u_char ivr; 507 508 union { 509 u_char b[4]; 510 u_short w[2]; 511 u_long l; 512 } data; 513 }; 514 #define dsp56k_host_interface ((*(volatile struct DSP56K_HOST_INTERFACE *)DSP56K_HOST_INTERFACE_BASE)) 515 516 /* 517 ** MFP 68901 518 */ 519 520 #define MFP_BAS (0xfffffa01) 521 struct MFP 522 { 523 u_char par_dt_reg; 524 u_char char_dummy1; 525 u_char active_edge; 526 u_char char_dummy2; 527 u_char data_dir; 528 u_char char_dummy3; 529 u_char int_en_a; 530 u_char char_dummy4; 531 u_char int_en_b; 532 u_char char_dummy5; 533 u_char int_pn_a; 534 u_char char_dummy6; 535 u_char int_pn_b; 536 u_char char_dummy7; 537 u_char int_sv_a; 538 u_char char_dummy8; 539 u_char int_sv_b; 540 u_char char_dummy9; 541 u_char int_mk_a; 542 u_char char_dummy10; 543 u_char int_mk_b; 544 u_char char_dummy11; 545 u_char vec_adr; 546 u_char char_dummy12; 547 u_char tim_ct_a; 548 u_char char_dummy13; 549 u_char tim_ct_b; 550 u_char char_dummy14; 551 u_char tim_ct_cd; 552 u_char char_dummy15; 553 u_char tim_dt_a; 554 u_char char_dummy16; 555 u_char tim_dt_b; 556 u_char char_dummy17; 557 u_char tim_dt_c; 558 u_char char_dummy18; 559 u_char tim_dt_d; 560 u_char char_dummy19; 561 u_char sync_char; 562 u_char char_dummy20; 563 u_char usart_ctr; 564 u_char char_dummy21; 565 u_char rcv_stat; 566 u_char char_dummy22; 567 u_char trn_stat; 568 u_char char_dummy23; 569 u_char usart_dta; 570 }; 571 # define st_mfp ((*(volatile struct MFP*)MFP_BAS)) 572 573 /* TT's second MFP */ 574 575 #define TT_MFP_BAS (0xfffffa81) 576 # define tt_mfp ((*(volatile struct MFP*)TT_MFP_BAS)) 577 578 579 /* TT System Control Unit */ 580 581 #define TT_SCU_BAS (0xffff8e01) 582 struct TT_SCU { 583 u_char sys_mask; 584 u_char char_dummy1; 585 u_char sys_stat; 586 u_char char_dummy2; 587 u_char softint; 588 u_char char_dummy3; 589 u_char vmeint; 590 u_char char_dummy4; 591 u_char gp_reg1; 592 u_char char_dummy5; 593 u_char gp_reg2; 594 u_char char_dummy6; 595 u_char vme_mask; 596 u_char char_dummy7; 597 u_char vme_stat; 598 }; 599 #define tt_scu ((*(volatile struct TT_SCU *)TT_SCU_BAS)) 600 601 /* TT real time clock */ 602 603 #define TT_RTC_BAS (0xffff8961) 604 struct TT_RTC { 605 u_char regsel; 606 u_char dummy; 607 u_char data; 608 }; 609 #define tt_rtc ((*(volatile struct TT_RTC *)TT_RTC_BAS)) 610 611 612 /* 613 ** ACIA 6850 614 */ 615 /* constants for the ACIA registers */ 616 617 /* baudrate selection and reset (Baudrate = clock/factor) */ 618 #define ACIA_DIV1 0 619 #define ACIA_DIV16 1 620 #define ACIA_DIV64 2 621 #define ACIA_RESET 3 622 623 /* character format */ 624 #define ACIA_D7E2S (0<<2) /* 7 data, even parity, 2 stop */ 625 #define ACIA_D7O2S (1<<2) /* 7 data, odd parity, 2 stop */ 626 #define ACIA_D7E1S (2<<2) /* 7 data, even parity, 1 stop */ 627 #define ACIA_D7O1S (3<<2) /* 7 data, odd parity, 1 stop */ 628 #define ACIA_D8N2S (4<<2) /* 8 data, no parity, 2 stop */ 629 #define ACIA_D8N1S (5<<2) /* 8 data, no parity, 1 stop */ 630 #define ACIA_D8E1S (6<<2) /* 8 data, even parity, 1 stop */ 631 #define ACIA_D8O1S (7<<2) /* 8 data, odd parity, 1 stop */ 632 633 /* transmit control */ 634 #define ACIA_RLTID (0<<5) /* RTS low, TxINT disabled */ 635 #define ACIA_RLTIE (1<<5) /* RTS low, TxINT enabled */ 636 #define ACIA_RHTID (2<<5) /* RTS high, TxINT disabled */ 637 #define ACIA_RLTIDSB (3<<5) /* RTS low, TxINT disabled, send break */ 638 639 /* receive control */ 640 #define ACIA_RID (0<<7) /* RxINT disabled */ 641 #define ACIA_RIE (1<<7) /* RxINT enabled */ 642 643 /* status fields of the ACIA */ 644 #define ACIA_RDRF 1 /* Receive Data Register Full */ 645 #define ACIA_TDRE (1<<1) /* Transmit Data Register Empty */ 646 #define ACIA_DCD (1<<2) /* Data Carrier Detect */ 647 #define ACIA_CTS (1<<3) /* Clear To Send */ 648 #define ACIA_FE (1<<4) /* Framing Error */ 649 #define ACIA_OVRN (1<<5) /* Receiver Overrun */ 650 #define ACIA_PE (1<<6) /* Parity Error */ 651 #define ACIA_IRQ (1<<7) /* Interrupt Request */ 652 653 #define ACIA_BAS (0xfffffc00) 654 struct ACIA 655 { 656 u_char key_ctrl; 657 u_char char_dummy1; 658 u_char key_data; 659 u_char char_dummy2; 660 u_char mid_ctrl; 661 u_char char_dummy3; 662 u_char mid_data; 663 }; 664 # define acia ((*(volatile struct ACIA*)ACIA_BAS)) 665 666 #define TT_DMASND_BAS (0xffff8900) 667 struct TT_DMASND { 668 u_char int_ctrl; /* Falcon: Interrupt control */ 669 u_char ctrl; 670 u_char pad2; 671 u_char bas_hi; 672 u_char pad3; 673 u_char bas_mid; 674 u_char pad4; 675 u_char bas_low; 676 u_char pad5; 677 u_char addr_hi; 678 u_char pad6; 679 u_char addr_mid; 680 u_char pad7; 681 u_char addr_low; 682 u_char pad8; 683 u_char end_hi; 684 u_char pad9; 685 u_char end_mid; 686 u_char pad10; 687 u_char end_low; 688 u_char pad11[12]; 689 u_char track_select; /* Falcon */ 690 u_char mode; 691 u_char pad12[14]; 692 /* Falcon only: */ 693 u_short cbar_src; 694 u_short cbar_dst; 695 u_char ext_div; 696 u_char int_div; 697 u_char rec_track_select; 698 u_char dac_src; 699 u_char adc_src; 700 u_char input_gain; 701 u_short output_atten; 702 }; 703 # define tt_dmasnd ((*(volatile struct TT_DMASND *)TT_DMASND_BAS)) 704 705 #define DMASND_MFP_INT_REPLAY 0x01 706 #define DMASND_MFP_INT_RECORD 0x02 707 #define DMASND_TIMERA_INT_REPLAY 0x04 708 #define DMASND_TIMERA_INT_RECORD 0x08 709 710 #define DMASND_CTRL_OFF 0x00 711 #define DMASND_CTRL_ON 0x01 712 #define DMASND_CTRL_REPEAT 0x02 713 #define DMASND_CTRL_RECORD_ON 0x10 714 #define DMASND_CTRL_RECORD_OFF 0x00 715 #define DMASND_CTRL_RECORD_REPEAT 0x20 716 #define DMASND_CTRL_SELECT_REPLAY 0x00 717 #define DMASND_CTRL_SELECT_RECORD 0x80 718 #define DMASND_MODE_MONO 0x80 719 #define DMASND_MODE_STEREO 0x00 720 #define DMASND_MODE_8BIT 0x00 721 #define DMASND_MODE_16BIT 0x40 /* Falcon only */ 722 #define DMASND_MODE_6KHZ 0x00 /* Falcon: mute */ 723 #define DMASND_MODE_12KHZ 0x01 724 #define DMASND_MODE_25KHZ 0x02 725 #define DMASND_MODE_50KHZ 0x03 726 727 728 #define DMASNDSetBase(bufstart) \ 729 do { \ 730 tt_dmasnd.bas_hi = (unsigned char)(((bufstart) & 0xff0000) >> 16); \ 731 tt_dmasnd.bas_mid = (unsigned char)(((bufstart) & 0x00ff00) >> 8); \ 732 tt_dmasnd.bas_low = (unsigned char) ((bufstart) & 0x0000ff); \ 733 } while( 0 ) 734 735 #define DMASNDGetAdr() ((tt_dmasnd.addr_hi << 16) + \ 736 (tt_dmasnd.addr_mid << 8) + \ 737 (tt_dmasnd.addr_low)) 738 739 #define DMASNDSetEnd(bufend) \ 740 do { \ 741 tt_dmasnd.end_hi = (unsigned char)(((bufend) & 0xff0000) >> 16); \ 742 tt_dmasnd.end_mid = (unsigned char)(((bufend) & 0x00ff00) >> 8); \ 743 tt_dmasnd.end_low = (unsigned char) ((bufend) & 0x0000ff); \ 744 } while( 0 ) 745 746 747 #define TT_MICROWIRE_BAS (0xffff8922) 748 struct TT_MICROWIRE { 749 u_short data; 750 u_short mask; 751 }; 752 # define tt_microwire ((*(volatile struct TT_MICROWIRE *)TT_MICROWIRE_BAS)) 753 754 #define MW_LM1992_ADDR 0x0400 755 756 #define MW_LM1992_VOLUME(dB) \ 757 (0x0c0 | ((dB) < -80 ? 0 : (dB) > 0 ? 40 : (((dB) + 80) / 2))) 758 #define MW_LM1992_BALLEFT(dB) \ 759 (0x140 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2))) 760 #define MW_LM1992_BALRIGHT(dB) \ 761 (0x100 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2))) 762 #define MW_LM1992_TREBLE(dB) \ 763 (0x080 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6))) 764 #define MW_LM1992_BASS(dB) \ 765 (0x040 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6))) 766 767 #define MW_LM1992_PSG_LOW 0x000 768 #define MW_LM1992_PSG_HIGH 0x001 769 #define MW_LM1992_PSG_OFF 0x002 770 771 #define MSTE_RTC_BAS (0xfffffc21) 772 773 struct MSTE_RTC { 774 u_char sec_ones; 775 u_char dummy1; 776 u_char sec_tens; 777 u_char dummy2; 778 u_char min_ones; 779 u_char dummy3; 780 u_char min_tens; 781 u_char dummy4; 782 u_char hr_ones; 783 u_char dummy5; 784 u_char hr_tens; 785 u_char dummy6; 786 u_char weekday; 787 u_char dummy7; 788 u_char day_ones; 789 u_char dummy8; 790 u_char day_tens; 791 u_char dummy9; 792 u_char mon_ones; 793 u_char dummy10; 794 u_char mon_tens; 795 u_char dummy11; 796 u_char year_ones; 797 u_char dummy12; 798 u_char year_tens; 799 u_char dummy13; 800 u_char mode; 801 u_char dummy14; 802 u_char test; 803 u_char dummy15; 804 u_char reset; 805 }; 806 807 #define mste_rtc ((*(volatile struct MSTE_RTC *)MSTE_RTC_BAS)) 808 809 /* 810 ** EtherNAT add-on card for Falcon - combined ethernet and USB adapter 811 */ 812 813 #define ATARI_ETHERNAT_PHYS_ADDR 0x80000000 814 815 #endif /* linux/atarihw.h */ 816 817