1 /***************************************************************************/ 2 3 /* 4 * m54xx.c -- platform support for ColdFire 54xx based boards 5 * 6 * Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be> 7 */ 8 9 /***************************************************************************/ 10 11 #include <linux/kernel.h> 12 #include <linux/param.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/mm.h> 17 #include <linux/clk.h> 18 #include <linux/bootmem.h> 19 #include <asm/pgalloc.h> 20 #include <asm/machdep.h> 21 #include <asm/coldfire.h> 22 #include <asm/m54xxsim.h> 23 #include <asm/mcfuart.h> 24 #include <asm/mcfclk.h> 25 #include <asm/m54xxgpt.h> 26 #ifdef CONFIG_MMU 27 #include <asm/mmu_context.h> 28 #endif 29 30 /***************************************************************************/ 31 32 DEFINE_CLK(pll, "pll.0", MCF_CLK); 33 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); 34 DEFINE_CLK(mcfslt0, "mcfslt.0", MCF_BUSCLK); 35 DEFINE_CLK(mcfslt1, "mcfslt.1", MCF_BUSCLK); 36 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); 37 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); 38 DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); 39 DEFINE_CLK(mcfuart3, "mcfuart.3", MCF_BUSCLK); 40 DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK); 41 42 struct clk *mcf_clks[] = { 43 &clk_pll, 44 &clk_sys, 45 &clk_mcfslt0, 46 &clk_mcfslt1, 47 &clk_mcfuart0, 48 &clk_mcfuart1, 49 &clk_mcfuart2, 50 &clk_mcfuart3, 51 &clk_mcfi2c0, 52 NULL 53 }; 54 55 /***************************************************************************/ 56 57 static void __init m54xx_uarts_init(void) 58 { 59 /* enable io pins */ 60 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0); 61 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS, 62 MCFGPIO_PAR_PSC1); 63 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS | 64 MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2); 65 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3); 66 } 67 68 /***************************************************************************/ 69 70 static void __init m54xx_i2c_init(void) 71 { 72 #if IS_ENABLED(CONFIG_I2C_IMX) 73 u32 r; 74 75 /* set the fec/i2c/irq pin assignment register for i2c */ 76 r = readl(MCF_PAR_FECI2CIRQ); 77 r |= MCF_PAR_FECI2CIRQ_SDA | MCF_PAR_FECI2CIRQ_SCL; 78 writel(r, MCF_PAR_FECI2CIRQ); 79 #endif /* IS_ENABLED(CONFIG_I2C_IMX) */ 80 } 81 82 /***************************************************************************/ 83 84 static void mcf54xx_reset(void) 85 { 86 /* disable interrupts and enable the watchdog */ 87 asm("movew #0x2700, %sr\n"); 88 __raw_writel(0, MCF_GPT_GMS0); 89 __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0); 90 __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4), 91 MCF_GPT_GMS0); 92 } 93 94 /***************************************************************************/ 95 96 void __init config_BSP(char *commandp, int size) 97 { 98 #ifdef CONFIG_MMU 99 cf_bootmem_alloc(); 100 mmu_context_init(); 101 #endif 102 mach_reset = mcf54xx_reset; 103 mach_sched_init = hw_timer_init; 104 m54xx_uarts_init(); 105 m54xx_i2c_init(); 106 } 107 108 /***************************************************************************/ 109