1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * m5441x.c -- support for Coldfire m5441x processors 4 * 5 * (C) Copyright Steven King <sfking@fdwdc.com> 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/param.h> 10 #include <linux/init.h> 11 #include <linux/io.h> 12 #include <linux/clk.h> 13 #include <asm/machdep.h> 14 #include <asm/coldfire.h> 15 #include <asm/mcfsim.h> 16 #include <asm/mcfuart.h> 17 #include <asm/mcfdma.h> 18 #include <asm/mcfclk.h> 19 20 DEFINE_CLK(0, "flexbus", 2, MCF_CLK); 21 DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK); 22 DEFINE_CLK(0, "mcfcan.1", 9, MCF_CLK); 23 DEFINE_CLK(0, "imx1-i2c.1", 14, MCF_CLK); 24 DEFINE_CLK(0, "mcfdspi.1", 15, MCF_CLK); 25 DEFINE_CLK(0, "edma", 17, MCF_CLK); 26 DEFINE_CLK(0, "intc.0", 18, MCF_CLK); 27 DEFINE_CLK(0, "intc.1", 19, MCF_CLK); 28 DEFINE_CLK(0, "intc.2", 20, MCF_CLK); 29 DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK); 30 DEFINE_CLK(0, "fsl-dspi.0", 23, MCF_CLK); 31 DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK); 32 DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK); 33 DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK); 34 DEFINE_CLK(0, "mcfuart.3", 27, MCF_BUSCLK); 35 DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK); 36 DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK); 37 DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK); 38 DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK); 39 DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK); 40 DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK); 41 DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK); 42 DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK); 43 DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK); 44 DEFINE_CLK(0, "mcfadc.0", 38, MCF_CLK); 45 DEFINE_CLK(0, "mcfdac.0", 39, MCF_CLK); 46 DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK); 47 DEFINE_CLK(0, "mcfsim.0", 43, MCF_CLK); 48 DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK); 49 DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK); 50 DEFINE_CLK(0, "mcfddr-sram.0", 46, MCF_CLK); 51 DEFINE_CLK(0, "mcfssi.0", 47, MCF_CLK); 52 DEFINE_CLK(0, "pll.0", 48, MCF_CLK); 53 DEFINE_CLK(0, "mcfrng.0", 49, MCF_CLK); 54 DEFINE_CLK(0, "mcfssi.1", 50, MCF_CLK); 55 DEFINE_CLK(0, "sdhci-esdhc-mcf.0", 51, MCF_CLK); 56 DEFINE_CLK(0, "enet-fec.0", 53, MCF_CLK); 57 DEFINE_CLK(0, "enet-fec.1", 54, MCF_CLK); 58 DEFINE_CLK(0, "switch.0", 55, MCF_CLK); 59 DEFINE_CLK(0, "switch.1", 56, MCF_CLK); 60 DEFINE_CLK(0, "nand.0", 63, MCF_CLK); 61 62 DEFINE_CLK(1, "mcfow.0", 2, MCF_CLK); 63 DEFINE_CLK(1, "imx1-i2c.2", 4, MCF_CLK); 64 DEFINE_CLK(1, "imx1-i2c.3", 5, MCF_CLK); 65 DEFINE_CLK(1, "imx1-i2c.4", 6, MCF_CLK); 66 DEFINE_CLK(1, "imx1-i2c.5", 7, MCF_CLK); 67 DEFINE_CLK(1, "mcfuart.4", 24, MCF_BUSCLK); 68 DEFINE_CLK(1, "mcfuart.5", 25, MCF_BUSCLK); 69 DEFINE_CLK(1, "mcfuart.6", 26, MCF_BUSCLK); 70 DEFINE_CLK(1, "mcfuart.7", 27, MCF_BUSCLK); 71 DEFINE_CLK(1, "mcfuart.8", 28, MCF_BUSCLK); 72 DEFINE_CLK(1, "mcfuart.9", 29, MCF_BUSCLK); 73 DEFINE_CLK(1, "mcfpwm.0", 34, MCF_BUSCLK); 74 DEFINE_CLK(1, "sys.0", 36, MCF_BUSCLK); 75 DEFINE_CLK(1, "gpio.0", 37, MCF_BUSCLK); 76 77 DEFINE_CLK(2, "ipg.0", 0, MCF_CLK); 78 DEFINE_CLK(2, "ahb.0", 1, MCF_CLK); 79 DEFINE_CLK(2, "per.0", 2, MCF_CLK); 80 81 struct clk *mcf_clks[] = { 82 &__clk_0_2, 83 &__clk_0_8, 84 &__clk_0_9, 85 &__clk_0_14, 86 &__clk_0_15, 87 &__clk_0_17, 88 &__clk_0_18, 89 &__clk_0_19, 90 &__clk_0_20, 91 &__clk_0_22, 92 &__clk_0_23, 93 &__clk_0_24, 94 &__clk_0_25, 95 &__clk_0_26, 96 &__clk_0_27, 97 &__clk_0_28, 98 &__clk_0_29, 99 &__clk_0_30, 100 &__clk_0_31, 101 &__clk_0_32, 102 &__clk_0_33, 103 &__clk_0_34, 104 &__clk_0_35, 105 &__clk_0_37, 106 &__clk_0_38, 107 &__clk_0_39, 108 &__clk_0_42, 109 &__clk_0_43, 110 &__clk_0_44, 111 &__clk_0_45, 112 &__clk_0_46, 113 &__clk_0_47, 114 &__clk_0_48, 115 &__clk_0_49, 116 &__clk_0_50, 117 &__clk_0_51, 118 &__clk_0_53, 119 &__clk_0_54, 120 &__clk_0_55, 121 &__clk_0_56, 122 &__clk_0_63, 123 124 &__clk_1_2, 125 &__clk_1_4, 126 &__clk_1_5, 127 &__clk_1_6, 128 &__clk_1_7, 129 &__clk_1_24, 130 &__clk_1_25, 131 &__clk_1_26, 132 &__clk_1_27, 133 &__clk_1_28, 134 &__clk_1_29, 135 &__clk_1_34, 136 &__clk_1_36, 137 &__clk_1_37, 138 139 &__clk_2_0, 140 &__clk_2_1, 141 &__clk_2_2, 142 143 NULL, 144 }; 145 146 147 static struct clk * const enable_clks[] __initconst = { 148 /* make sure these clocks are enabled */ 149 &__clk_0_15, /* dspi.1 */ 150 &__clk_0_17, /* eDMA */ 151 &__clk_0_18, /* intc0 */ 152 &__clk_0_19, /* intc0 */ 153 &__clk_0_20, /* intc0 */ 154 &__clk_0_23, /* dspi.0 */ 155 &__clk_0_24, /* uart0 */ 156 &__clk_0_25, /* uart1 */ 157 &__clk_0_26, /* uart2 */ 158 &__clk_0_27, /* uart3 */ 159 160 &__clk_0_33, /* pit.1 */ 161 &__clk_0_37, /* eport */ 162 &__clk_0_48, /* pll */ 163 &__clk_0_51, /* esdhc */ 164 165 &__clk_1_36, /* CCM/reset module/Power management */ 166 &__clk_1_37, /* gpio */ 167 }; 168 static struct clk * const disable_clks[] __initconst = { 169 &__clk_0_8, /* can.0 */ 170 &__clk_0_9, /* can.1 */ 171 &__clk_0_14, /* i2c.1 */ 172 &__clk_0_22, /* i2c.0 */ 173 &__clk_0_23, /* dspi.0 */ 174 &__clk_0_28, /* tmr.1 */ 175 &__clk_0_29, /* tmr.2 */ 176 &__clk_0_30, /* tmr.2 */ 177 &__clk_0_31, /* tmr.3 */ 178 &__clk_0_32, /* pit.0 */ 179 &__clk_0_34, /* pit.2 */ 180 &__clk_0_35, /* pit.3 */ 181 &__clk_0_38, /* adc */ 182 &__clk_0_39, /* dac */ 183 &__clk_0_44, /* usb otg */ 184 &__clk_0_45, /* usb host */ 185 &__clk_0_47, /* ssi.0 */ 186 &__clk_0_49, /* rng */ 187 &__clk_0_50, /* ssi.1 */ 188 &__clk_0_51, /* eSDHC */ 189 &__clk_0_53, /* enet-fec */ 190 &__clk_0_54, /* enet-fec */ 191 &__clk_0_55, /* switch.0 */ 192 &__clk_0_56, /* switch.1 */ 193 194 &__clk_1_2, /* 1-wire */ 195 &__clk_1_4, /* i2c.2 */ 196 &__clk_1_5, /* i2c.3 */ 197 &__clk_1_6, /* i2c.4 */ 198 &__clk_1_7, /* i2c.5 */ 199 &__clk_1_24, /* uart 4 */ 200 &__clk_1_25, /* uart 5 */ 201 &__clk_1_26, /* uart 6 */ 202 &__clk_1_27, /* uart 7 */ 203 &__clk_1_28, /* uart 8 */ 204 &__clk_1_29, /* uart 9 */ 205 }; 206 207 static void __clk_enable2(struct clk *clk) 208 { 209 __raw_writel(__raw_readl(MCFSDHC_CLK) | (1 << clk->slot), MCFSDHC_CLK); 210 } 211 212 static void __clk_disable2(struct clk *clk) 213 { 214 __raw_writel(__raw_readl(MCFSDHC_CLK) & ~(1 << clk->slot), MCFSDHC_CLK); 215 } 216 217 struct clk_ops clk_ops2 = { 218 .enable = __clk_enable2, 219 .disable = __clk_disable2, 220 }; 221 222 static void __init m5441x_clk_init(void) 223 { 224 unsigned i; 225 226 for (i = 0; i < ARRAY_SIZE(enable_clks); ++i) 227 __clk_init_enabled(enable_clks[i]); 228 /* make sure these clocks are disabled */ 229 for (i = 0; i < ARRAY_SIZE(disable_clks); ++i) 230 __clk_init_disabled(disable_clks[i]); 231 } 232 233 static void __init m5441x_uarts_init(void) 234 { 235 __raw_writeb(0x0f, MCFGPIO_PAR_UART0); 236 __raw_writeb(0x00, MCFGPIO_PAR_UART1); 237 __raw_writeb(0x00, MCFGPIO_PAR_UART2); 238 } 239 240 static void __init m5441x_fec_init(void) 241 { 242 __raw_writeb(0x03, MCFGPIO_PAR_FEC); 243 } 244 245 void __init config_BSP(char *commandp, int size) 246 { 247 m5441x_clk_init(); 248 mach_sched_init = hw_timer_init; 249 m5441x_uarts_init(); 250 m5441x_fec_init(); 251 } 252