xref: /openbmc/linux/arch/m68k/coldfire/m528x.c (revision 82003e04)
1 /***************************************************************************/
2 
3 /*
4  *	m528x.c  -- platform support for ColdFire 528x based boards
5  *
6  *	Sub-architcture dependent initialization code for the Freescale
7  *	5280, 5281 and 5282 CPUs.
8  *
9  *	Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
10  *	Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
11  */
12 
13 /***************************************************************************/
14 
15 #include <linux/kernel.h>
16 #include <linux/param.h>
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/io.h>
20 #include <asm/machdep.h>
21 #include <asm/coldfire.h>
22 #include <asm/mcfsim.h>
23 #include <asm/mcfuart.h>
24 #include <asm/mcfclk.h>
25 
26 /***************************************************************************/
27 
28 DEFINE_CLK(pll, "pll.0", MCF_CLK);
29 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
30 DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
31 DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
32 DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
33 DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
34 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
35 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
36 DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
37 DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
38 DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
39 
40 struct clk *mcf_clks[] = {
41 	&clk_pll,
42 	&clk_sys,
43 	&clk_mcfpit0,
44 	&clk_mcfpit1,
45 	&clk_mcfpit2,
46 	&clk_mcfpit3,
47 	&clk_mcfuart0,
48 	&clk_mcfuart1,
49 	&clk_mcfuart2,
50 	&clk_mcfqspi0,
51 	&clk_fec0,
52 	NULL
53 };
54 
55 /***************************************************************************/
56 
57 static void __init m528x_qspi_init(void)
58 {
59 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
60 	/* setup Port QS for QSPI with gpio CS control */
61 	__raw_writeb(0x07, MCFGPIO_PQSPAR);
62 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
63 }
64 
65 /***************************************************************************/
66 
67 static void __init m528x_uarts_init(void)
68 {
69 	u8 port;
70 
71 	/* make sure PUAPAR is set for UART0 and UART1 */
72 	port = readb(MCFGPIO_PUAPAR);
73 	port |= 0x03 | (0x03 << 2);
74 	writeb(port, MCFGPIO_PUAPAR);
75 }
76 
77 /***************************************************************************/
78 
79 static void __init m528x_fec_init(void)
80 {
81 	u16 v16;
82 
83 	/* Set multi-function pins to ethernet mode for fec0 */
84 	v16 = readw(MCFGPIO_PASPAR);
85 	writew(v16 | 0xf00, MCFGPIO_PASPAR);
86 	writeb(0xc0, MCFGPIO_PEHLPAR);
87 }
88 
89 /***************************************************************************/
90 
91 #ifdef CONFIG_WILDFIRE
92 void wildfire_halt(void)
93 {
94 	writeb(0, 0x30000007);
95 	writeb(0x2, 0x30000007);
96 }
97 #endif
98 
99 #ifdef CONFIG_WILDFIREMOD
100 void wildfiremod_halt(void)
101 {
102 	printk(KERN_INFO "WildFireMod hibernating...\n");
103 
104 	/* Set portE.5 to Digital IO */
105 	writew(readw(MCFGPIO_PEPAR) & ~(1 << (5 * 2)), MCFGPIO_PEPAR);
106 
107 	/* Make portE.5 an output */
108 	writeb(readb(MCFGPIO_PDDR_E) | (1 << 5), MCFGPIO_PDDR_E);
109 
110 	/* Now toggle portE.5 from low to high */
111 	writeb(readb(MCFGPIO_PODR_E) & ~(1 << 5), MCFGPIO_PODR_E);
112 	writeb(readb(MCFGPIO_PODR_E) | (1 << 5), MCFGPIO_PODR_E);
113 
114 	printk(KERN_EMERG "Failed to hibernate. Halting!\n");
115 }
116 #endif
117 
118 void __init config_BSP(char *commandp, int size)
119 {
120 #ifdef CONFIG_WILDFIRE
121 	mach_halt = wildfire_halt;
122 #endif
123 #ifdef CONFIG_WILDFIREMOD
124 	mach_halt = wildfiremod_halt;
125 #endif
126 	mach_sched_init = hw_timer_init;
127 	m528x_uarts_init();
128 	m528x_fec_init();
129 	m528x_qspi_init();
130 }
131 
132 /***************************************************************************/
133