1# SPDX-License-Identifier: GPL-2.0 2comment "Processor Type" 3 4choice 5 prompt "CPU family support" 6 default M68KCLASSIC if MMU 7 default COLDFIRE if !MMU 8 help 9 The Freescale (was Motorola) M68K family of processors implements 10 the full 68000 processor instruction set. 11 The Freescale ColdFire family of processors is a modern derivative 12 of the 68000 processor family. They are mainly targeted at embedded 13 applications, and are all System-On-Chip (SOC) devices, as opposed 14 to stand alone CPUs. They implement a subset of the original 68000 15 processor instruction set. 16 If you anticipate running this kernel on a computer with a classic 17 MC68xxx processor, select M68KCLASSIC. 18 If you anticipate running this kernel on a computer with a ColdFire 19 processor, select COLDFIRE. 20 21config M68KCLASSIC 22 bool "Classic M68K CPU family support" 23 select HAVE_ARCH_PFN_VALID 24 25config COLDFIRE 26 bool "Coldfire CPU family support" 27 select ARCH_HAVE_CUSTOM_GPIO_H 28 select CPU_HAS_NO_BITFIELDS 29 select CPU_HAS_NO_MULDIV64 30 select GENERIC_CSUM 31 select GPIOLIB 32 select HAVE_LEGACY_CLK 33 34endchoice 35 36if M68KCLASSIC 37 38config M68000 39 bool "MC68000" 40 depends on !MMU 41 select CPU_HAS_NO_BITFIELDS 42 select CPU_HAS_NO_MULDIV64 43 select CPU_HAS_NO_UNALIGNED 44 select GENERIC_CSUM 45 select CPU_NO_EFFICIENT_FFS 46 select HAVE_ARCH_HASH 47 help 48 The Freescale (was Motorola) 68000 CPU is the first generation of 49 the well known M68K family of processors. The CPU core as well as 50 being available as a stand alone CPU was also used in many 51 System-On-Chip devices (eg 68328, 68302, etc). It does not contain 52 a paging MMU. 53 54config MCPU32 55 bool 56 select CPU_HAS_NO_BITFIELDS 57 select CPU_HAS_NO_UNALIGNED 58 select CPU_NO_EFFICIENT_FFS 59 help 60 The Freescale (was then Motorola) CPU32 is a CPU core that is 61 based on the 68020 processor. For the most part it is used in 62 System-On-Chip parts, and does not contain a paging MMU. 63 64config M68020 65 bool "68020 support" 66 depends on MMU 67 select FPU 68 select CPU_HAS_ADDRESS_SPACES 69 help 70 If you anticipate running this kernel on a computer with a MC68020 71 processor, say Y. Otherwise, say N. Note that the 68020 requires a 72 68851 MMU (Memory Management Unit) to run Linux/m68k, except on the 73 Sun 3, which provides its own version. 74 75config M68030 76 bool "68030 support" 77 depends on MMU && !MMU_SUN3 78 select FPU 79 select CPU_HAS_ADDRESS_SPACES 80 help 81 If you anticipate running this kernel on a computer with a MC68030 82 processor, say Y. Otherwise, say N. Note that a MC68EC030 will not 83 work, as it does not include an MMU (Memory Management Unit). 84 85config M68040 86 bool "68040 support" 87 depends on MMU && !MMU_SUN3 88 select FPU 89 select CPU_HAS_ADDRESS_SPACES 90 help 91 If you anticipate running this kernel on a computer with a MC68LC040 92 or MC68040 processor, say Y. Otherwise, say N. Note that an 93 MC68EC040 will not work, as it does not include an MMU (Memory 94 Management Unit). 95 96config M68060 97 bool "68060 support" 98 depends on MMU && !MMU_SUN3 99 select FPU 100 select CPU_HAS_ADDRESS_SPACES 101 help 102 If you anticipate running this kernel on a computer with a MC68060 103 processor, say Y. Otherwise, say N. 104 105config M68328 106 bool "MC68328" 107 depends on !MMU 108 select M68000 109 help 110 Motorola 68328 processor support. 111 112config M68EZ328 113 bool "MC68EZ328" 114 depends on !MMU 115 select M68000 116 help 117 Motorola 68EX328 processor support. 118 119config M68VZ328 120 bool "MC68VZ328" 121 depends on !MMU 122 select M68000 123 help 124 Motorola 68VZ328 processor support. 125 126endif # M68KCLASSIC 127 128if COLDFIRE 129 130choice 131 prompt "ColdFire SoC type" 132 default M520x 133 help 134 Select the type of ColdFire System-on-Chip (SoC) that you want 135 to build for. 136 137config M5206 138 bool "MCF5206" 139 depends on !MMU 140 select COLDFIRE_SW_A7 141 select HAVE_MBAR 142 select CPU_NO_EFFICIENT_FFS 143 help 144 Motorola ColdFire 5206 processor support. 145 146config M5206e 147 bool "MCF5206e" 148 depends on !MMU 149 select COLDFIRE_SW_A7 150 select HAVE_MBAR 151 select CPU_NO_EFFICIENT_FFS 152 help 153 Motorola ColdFire 5206e processor support. 154 155config M520x 156 bool "MCF520x" 157 depends on !MMU 158 select GENERIC_CLOCKEVENTS 159 select HAVE_CACHE_SPLIT 160 help 161 Freescale Coldfire 5207/5208 processor support. 162 163config M523x 164 bool "MCF523x" 165 depends on !MMU 166 select GENERIC_CLOCKEVENTS 167 select HAVE_CACHE_SPLIT 168 select HAVE_IPSBAR 169 help 170 Freescale Coldfire 5230/1/2/4/5 processor support 171 172config M5249 173 bool "MCF5249" 174 depends on !MMU 175 select COLDFIRE_SW_A7 176 select HAVE_MBAR 177 select CPU_NO_EFFICIENT_FFS 178 help 179 Motorola ColdFire 5249 processor support. 180 181config M525x 182 bool "MCF525x" 183 depends on !MMU 184 select COLDFIRE_SW_A7 185 select HAVE_MBAR 186 select CPU_NO_EFFICIENT_FFS 187 help 188 Freescale (Motorola) Coldfire 5251/5253 processor support. 189 190config M5271 191 bool "MCF5271" 192 depends on !MMU 193 select M527x 194 select HAVE_CACHE_SPLIT 195 select HAVE_IPSBAR 196 select GENERIC_CLOCKEVENTS 197 help 198 Freescale (Motorola) ColdFire 5270/5271 processor support. 199 200config M5272 201 bool "MCF5272" 202 depends on !MMU 203 select COLDFIRE_SW_A7 204 select HAVE_MBAR 205 select CPU_NO_EFFICIENT_FFS 206 help 207 Motorola ColdFire 5272 processor support. 208 209config M5275 210 bool "MCF5275" 211 depends on !MMU 212 select M527x 213 select HAVE_CACHE_SPLIT 214 select HAVE_IPSBAR 215 select GENERIC_CLOCKEVENTS 216 help 217 Freescale (Motorola) ColdFire 5274/5275 processor support. 218 219config M528x 220 bool "MCF528x" 221 depends on !MMU 222 select GENERIC_CLOCKEVENTS 223 select HAVE_CACHE_SPLIT 224 select HAVE_IPSBAR 225 help 226 Motorola ColdFire 5280/5282 processor support. 227 228config M5307 229 bool "MCF5307" 230 depends on !MMU 231 select COLDFIRE_SW_A7 232 select HAVE_CACHE_CB 233 select HAVE_MBAR 234 select CPU_NO_EFFICIENT_FFS 235 help 236 Motorola ColdFire 5307 processor support. 237 238config M532x 239 bool "MCF532x" 240 depends on !MMU 241 select M53xx 242 select HAVE_CACHE_CB 243 help 244 Freescale (Motorola) ColdFire 532x processor support. 245 246config M537x 247 bool "MCF537x" 248 depends on !MMU 249 select M53xx 250 select HAVE_CACHE_CB 251 help 252 Freescale ColdFire 537x processor support. 253 254config M5407 255 bool "MCF5407" 256 depends on !MMU 257 select COLDFIRE_SW_A7 258 select HAVE_CACHE_CB 259 select HAVE_MBAR 260 select CPU_NO_EFFICIENT_FFS 261 help 262 Motorola ColdFire 5407 processor support. 263 264config M547x 265 bool "MCF547x" 266 select M54xx 267 select MMU_COLDFIRE if MMU 268 select FPU if MMU 269 select HAVE_CACHE_CB 270 select HAVE_MBAR 271 select CPU_NO_EFFICIENT_FFS 272 help 273 Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support. 274 275config M548x 276 bool "MCF548x" 277 select MMU_COLDFIRE if MMU 278 select FPU if MMU 279 select M54xx 280 select HAVE_CACHE_CB 281 select HAVE_MBAR 282 select CPU_NO_EFFICIENT_FFS 283 help 284 Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support. 285 286config M5441x 287 bool "MCF5441x" 288 select MMU_COLDFIRE if MMU 289 select GENERIC_CLOCKEVENTS 290 select HAVE_CACHE_CB 291 help 292 Freescale Coldfire 54410/54415/54416/54417/54418 processor support. 293 294endchoice 295 296config M527x 297 bool 298 299config M53xx 300 bool 301 302config M54xx 303 select HAVE_PCI 304 bool 305 306endif # COLDFIRE 307 308 309comment "Processor Specific Options" 310 311config M68KFPU_EMU 312 bool "Math emulation support" 313 depends on MMU 314 help 315 At some point in the future, this will cause floating-point math 316 instructions to be emulated by the kernel on machines that lack a 317 floating-point math coprocessor. Thrill-seekers and chronically 318 sleep-deprived psychotic hacker types can say Y now, everyone else 319 should probably wait a while. 320 321config M68KFPU_EMU_EXTRAPREC 322 bool "Math emulation extra precision" 323 depends on M68KFPU_EMU 324 help 325 The fpu uses normally a few bit more during calculations for 326 correct rounding, the emulator can (often) do the same but this 327 extra calculation can cost quite some time, so you can disable 328 it here. The emulator will then "only" calculate with a 64 bit 329 mantissa and round slightly incorrect, what is more than enough 330 for normal usage. 331 332config M68KFPU_EMU_ONLY 333 bool "Math emulation only kernel" 334 depends on M68KFPU_EMU 335 help 336 This option prevents any floating-point instructions from being 337 compiled into the kernel, thereby the kernel doesn't save any 338 floating point context anymore during task switches, so this 339 kernel will only be usable on machines without a floating-point 340 math coprocessor. This makes the kernel a bit faster as no tests 341 needs to be executed whether a floating-point instruction in the 342 kernel should be executed or not. 343 344config ADVANCED 345 bool "Advanced configuration options" 346 depends on MMU 347 help 348 This gives you access to some advanced options for the CPU. The 349 defaults should be fine for most users, but these options may make 350 it possible for you to improve performance somewhat if you know what 351 you are doing. 352 353 Note that the answer to this question won't directly affect the 354 kernel: saying N will just cause the configurator to skip all 355 the questions about these options. 356 357 Most users should say N to this question. 358 359config RMW_INSNS 360 bool "Use read-modify-write instructions" 361 depends on ADVANCED 362 help 363 This allows to use certain instructions that work with indivisible 364 read-modify-write bus cycles. While this is faster than the 365 workaround of disabling interrupts, it can conflict with DMA 366 ( = direct memory access) on many Amiga systems, and it is also said 367 to destabilize other machines. It is very likely that this will 368 cause serious problems on any Amiga or Atari Medusa if set. The only 369 configuration where it should work are 68030-based Ataris, where it 370 apparently improves performance. But you've been warned! Unless you 371 really know what you are doing, say N. Try Y only if you're quite 372 adventurous. 373 374config SINGLE_MEMORY_CHUNK 375 bool "Use one physical chunk of memory only" if ADVANCED && !SUN3 376 depends on MMU 377 default y if SUN3 || MMU_COLDFIRE 378 help 379 Ignore all but the first contiguous chunk of physical memory for VM 380 purposes. This will save a few bytes kernel size and may speed up 381 some operations. 382 When this option os set to N, you may want to lower "Maximum zone 383 order" to save memory that could be wasted for unused memory map. 384 Say N if not sure. 385 386config ARCH_DISCONTIGMEM_ENABLE 387 depends on BROKEN 388 def_bool MMU && !SINGLE_MEMORY_CHUNK 389 390config FORCE_MAX_ZONEORDER 391 int "Maximum zone order" if ADVANCED 392 depends on !SINGLE_MEMORY_CHUNK 393 default "11" 394 help 395 The kernel memory allocator divides physically contiguous memory 396 blocks into "zones", where each zone is a power of two number of 397 pages. This option selects the largest power of two that the kernel 398 keeps in the memory allocator. If you need to allocate very large 399 blocks of physically contiguous memory, then you may need to 400 increase this value. 401 402 For systems that have holes in their physical address space this 403 value also defines the minimal size of the hole that allows 404 freeing unused memory map. 405 406 This config option is actually maximum order plus one. For example, 407 a value of 11 means that the largest free memory block is 2^10 pages. 408 409config 060_WRITETHROUGH 410 bool "Use write-through caching for 68060 supervisor accesses" 411 depends on ADVANCED && M68060 412 help 413 The 68060 generally uses copyback caching of recently accessed data. 414 Copyback caching means that memory writes will be held in an on-chip 415 cache and only written back to memory some time later. Saying Y 416 here will force supervisor (kernel) accesses to use writethrough 417 caching. Writethrough caching means that data is written to memory 418 straight away, so that cache and memory data always agree. 419 Writethrough caching is less efficient, but is needed for some 420 drivers on 68060 based systems where the 68060 bus snooping signal 421 is hardwired on. The 53c710 SCSI driver is known to suffer from 422 this problem. 423 424config M68K_L2_CACHE 425 bool 426 depends on MAC 427 default y 428 429config NODES_SHIFT 430 int 431 default "3" 432 depends on DISCONTIGMEM 433 434config CPU_HAS_NO_BITFIELDS 435 bool 436 437config CPU_HAS_NO_MULDIV64 438 bool 439 440config CPU_HAS_NO_UNALIGNED 441 bool 442 443config CPU_HAS_ADDRESS_SPACES 444 bool 445 446config FPU 447 bool 448 449config COLDFIRE_SW_A7 450 bool 451 452config HAVE_CACHE_SPLIT 453 bool 454 455config HAVE_CACHE_CB 456 bool 457 458config HAVE_MBAR 459 bool 460 461config HAVE_IPSBAR 462 bool 463 464config CLOCK_FREQ 465 int "Set the core clock frequency" 466 default "25000000" if M5206 467 default "54000000" if M5206e 468 default "166666666" if M520x 469 default "140000000" if M5249 470 default "150000000" if M527x || M523x 471 default "90000000" if M5307 472 default "50000000" if M5407 473 default "266000000" if M54xx 474 default "66666666" 475 depends on COLDFIRE 476 help 477 Define the CPU clock frequency in use. This is the core clock 478 frequency, it may or may not be the same as the external clock 479 crystal fitted to your board. Some processors have an internal 480 PLL and can have their frequency programmed at run time, others 481 use internal dividers. In general the kernel won't setup a PLL 482 if it is fitted (there are some exceptions). This value will be 483 specific to the exact CPU that you are using. 484 485config OLDMASK 486 bool "Old mask 5307 (1H55J) silicon" 487 depends on M5307 488 help 489 Build support for the older revision ColdFire 5307 silicon. 490 Specifically this is the 1H55J mask revision. 491 492if HAVE_CACHE_SPLIT 493choice 494 prompt "Split Cache Configuration" 495 default CACHE_I 496 497config CACHE_I 498 bool "Instruction" 499 help 500 Use all of the ColdFire CPU cache memory as an instruction cache. 501 502config CACHE_D 503 bool "Data" 504 help 505 Use all of the ColdFire CPU cache memory as a data cache. 506 507config CACHE_BOTH 508 bool "Both" 509 help 510 Split the ColdFire CPU cache, and use half as an instruction cache 511 and half as a data cache. 512endchoice 513endif 514 515if HAVE_CACHE_CB 516choice 517 prompt "Data cache mode" 518 default CACHE_WRITETHRU 519 520config CACHE_WRITETHRU 521 bool "Write-through" 522 help 523 The ColdFire CPU cache is set into Write-through mode. 524 525config CACHE_COPYBACK 526 bool "Copy-back" 527 help 528 The ColdFire CPU cache is set into Copy-back mode. 529endchoice 530endif 531 532